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51. 发明授权

US07227233B2 Silicon-on-insulator (SOI) Read Only Memory (ROM) array and method of making a SOI ROM 有权
标题翻译：绝缘体上硅（SOI）只读存储器（ROM）阵列和制造SOI ROM的方法
公开(公告)号：US07227233B2
公开(公告)日：2007-06-05
申请号：US11162472
申请日：2005-09-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Jack A. Mandelman
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Jack A. Mandelman
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/1203 , H01L27/1021 , H01L27/112 , H01L27/11213
摘要： A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.
摘要翻译：绝缘体上硅（SOI）只读存储器（ROM）以及制造SOI ROM的方法。 ROM单元位于导体层上的表面SOI层中的条纹与正交取向的导线之间的交叉处。电线的触点连接到条纹上表面的ROM单元二极管。 ROM单元个性化是存在或不存在二极管和/或接触。

52. 发明授权

US07087531B1 Shallow trench isolation formation 失效
公开(公告)号：US07087531B1
公开(公告)日：2006-08-08
申请号：US10905681
申请日：2005-01-17
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/72
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02282 , H01L21/3143 , H01L21/3147 , H01L21/316 , H01L21/76224 , H01L21/823878
摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

53. 发明授权

US06995065B2 Selective post-doping of gate structures by means of selective oxide growth 失效
公开(公告)号：US06995065B2
公开(公告)日：2006-02-07
申请号：US10732657
申请日：2003-12-10
申请人： Anthony I. Chou , Toshiharu Furukawa , Steven J. Holmes
发明人： Anthony I. Chou , Toshiharu Furukawa , Steven J. Holmes
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/02131 , H01L21/02164 , H01L21/02282 , H01L21/02304 , H01L21/266 , H01L21/316 , H01L21/31612 , H01L21/823814 , H01L21/823842 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

54. 发明授权

US06989323B2 Method for forming narrow gate structures on sidewalls of a lithographically defined sacrificial material 失效
标题翻译：在光刻定义的牺牲材料的侧壁上形成窄栅极结构的方法
公开(公告)号：US06989323B2
公开(公告)日：2006-01-24
申请号：US10709314
申请日：2004-04-28
申请人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823437 , H01L21/28097 , H01L21/28123 , H01L21/32139 , H01L29/4975
摘要： A method for forming a gate structure for a semiconductor device includes defining a conductive sacrificial structure on a substrate, forming a reacted metal film on sidewalls of the conductive sacrificial structure, and removing unreacted portions of the conductive sacrificial structure.
摘要翻译：用于形成半导体器件的栅极结构的方法包括在衬底上限定导电牺牲结构，在导电牺牲结构的侧壁上形成反应的金属膜，以及去除导电牺牲结构的未反应部分。

55. 发明授权

US06627361B2 Assist features for contact hole mask patterns 失效
标题翻译：辅助接触孔掩模图案的功能
公开(公告)号：US06627361B2
公开(公告)日：2003-09-30
申请号：US09901241
申请日：2001-07-09
申请人： Orest Bula , Michael S. Hibbs , Steven J. Holmes , Paul A. Rabidoux
发明人： Orest Bula , Michael S. Hibbs , Steven J. Holmes , Paul A. Rabidoux
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F7/095
摘要： An assist feature is formed on a lithographic reticle or mask using a hybrid resist and an exposure dose such that only an annular area is effectively exposed having a width that is potentially less than the minimum feature size that can be resolved by the mask exposure tool to simultaneously or sequentially form both a feature of interest and an assist feature for enhancing imaging of the feature of interest when the feature is printed to a wafer. Since the assist feature can be imaged simultaneously with the feature of interest or multiple assist features imaged concurrently, possibly between closely spaced features, data volume and mask writing time are greatly reduced. The invention is particularly applicable to the scaling of contact holes for connections to active devices in extremely high density integrated circuits.
摘要翻译：使用混合抗蚀剂和曝光剂量在光刻掩模版或掩模上形成辅助特征，使得只有环形区域被有效地暴露，其宽度可能小于可由掩模曝光工具解析的最小特征尺寸，同时或顺序地形成感兴趣的特征和当将特征印刷到晶片时增强感兴趣特征的成像的辅助特征。由于可以与感兴趣的特征或同时成像的多个辅助特征（可能在紧密间隔的特征之间）同时成像辅助特征，所以数据量和掩模写入时间被大大减少。本发明特别适用于用于连接到极高密度集成电路中的有源器件的接触孔的缩放。

56. 发明授权

US06620675B2 Increased capacitance trench capacitor 失效
标题翻译：增加电容沟槽电容
公开(公告)号：US06620675B2
公开(公告)日：2003-09-16
申请号：US09682607
申请日：2001-09-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , William H. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , William H. Ma
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , H01L28/87 , H01L29/945 , Y10S438/964
摘要： Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on the pits and the sidewall; and filling said trench with a trench conductor.
摘要翻译：公开了通过增加侧壁面积来增加沟槽电容器的电容的方法，包括：在硅衬底中形成沟槽，所述沟槽具有侧壁; 在沟槽的侧壁上形成岛; 并使用岛作为掩模将凹坑蚀刻到侧壁中。通过在凹坑和侧壁上形成节点绝缘体来完成电容器; 以及用沟槽导体填充所述沟槽。

57. 发明授权

US06489207B2 Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor 失效
公开(公告)号：US06489207B2
公开(公告)日：2002-12-03
申请号：US09871926
申请日：2001-06-01
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/223 , H01L21/2236 , H01L21/28035 , H01L21/28061 , H01L21/32 , H01L21/823814 , H01L21/823842
摘要： The present invention relates to a method of forming a very shallow source-drain (S/D) extension while simultaneously highly doping a very narrow polysilicon gate through to the gate dielectric interface. The invention also relates to the resulting semiconductor.

58. 发明授权

US06452265B1 Multi-chip module utilizing a nonconductive material surrounding the chips that has a similar coefficient of thermal expansion 失效
标题翻译：利用具有相似热膨胀系数的芯片周围的非导电材料的多芯片模块
公开(公告)号：US06452265B1
公开(公告)日：2002-09-17
申请号：US09493929
申请日：2000-01-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Rosemary A. Previti-Kelly , Edmund Sprogis
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Rosemary A. Previti-Kelly , Edmund Sprogis
IPC分类号： H01L2334
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3738 , H01L23/5389 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/73204 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/0401
摘要： A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.
摘要翻译：通过使支撑晶片上的预接线芯片对准并沉积具有接近芯片（例如硅，碳化硅，硅锗，锗或SiCGe）的热膨胀系数的非导电导热和非导电材料来构造多芯片模块）围绕芯片。拆卸支撑晶片后，多芯片模块的处理通过多芯片模块和芯片表面的共享表面上的布线完成。

59. 发明授权

US06444402B1 Method of making differently sized vias and lines on the same lithography level 失效
标题翻译：在相同光刻级别上制作不同尺寸的通孔和线的方法
公开(公告)号：US06444402B1
公开(公告)日：2002-09-03
申请号：US09532187
申请日：2000-03-21
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
IPC分类号： G03C500
CPC分类号： H01L21/31144 , G03F7/0035 , G03F7/40 , H01L21/0332 , H01L21/0337 , H01L21/76816
摘要： Features of two or more distinct sizes designed to optimize performance of an integrated circuit device are formed by transferring a pattern from a resist patterned with features of a single minimum feature size for which a resist exposure tool is optimized to a layer of preferably soluble material such as germanium oxide. Portions of this pattern are then enlarged using a block-out mask and the resulting pattern transferred to a further underlying layer preferably using an anisotropic reactive ion etch. The soluble material can then be removed leaving a robust mask with differing feature sizes for further processing. Preferably, Damascene conductive lines and vias are formed by providing an insulator as the further underlying material and filling the openings with metal or other conductive material.
摘要翻译：设计用于优化集成电路器件性能的两个或多个不同尺寸的特征通过将图案从具有抗蚀剂曝光工具优化的单个最小特征尺寸的特征的抗蚀剂转移到优选可溶性材料层而形成，作为氧化锗。然后使用阻挡掩模将该图案的部分放大，并且将所得到的图案优选地使用各向异性反应离子蚀刻转移到另一下层。然后可以去除可溶性材料，留下具有不同特征尺寸的坚固的掩模，用于进一步处理。优选地，通过提供绝缘体作为其他下层材料并用金属或其它导电材料填充开口来形成镶嵌导电线和通孔。

60. 发明授权

US06372412B1 Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed thereby 失效
标题翻译：使用倍频混合光致抗蚀剂制造集成电路芯片的方法和由此形成的装置
公开(公告)号：US06372412B1
公开(公告)日：2002-04-16
申请号：US09021924
申请日：1998-02-10
申请人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Ahmad D. Katnani , Niranjan M. Patel , Paul A. Rabidoux
发明人： Mark C. Hakey , Steven J. Holmes , David V. Horak , Ahmad D. Katnani , Niranjan M. Patel , Paul A. Rabidoux
IPC分类号： G03F730
CPC分类号： H01L28/82 , G03F7/0045 , G03F7/038 , G03F7/039 , G03F7/095 , H01L21/0274 , H01L21/3085
摘要： A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.
摘要翻译：公开了具有负色调和正色调响应的光致抗蚀剂组合物，在曝光到中等辐射能量的衍射区域中形成空间。该抗蚀剂材料可以用于印刷圆环形状或者可以进行第二掩蔽步骤以打印线。另外，可以使用掩模版中的灰度滤光片获得更大和更小的特征，以产生更大面积的中间曝光区域。

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