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    • 8. 发明授权
    • Process for fabricating short channel field effect transistor with a highly conductive gate
    • US06221704B1
    • 2001-04-24
    • US09089650
    • 1998-06-03
    • Toshiharu FurukawaMark C. HakeySteven J. HolmesDavid V. HorakJames S. NakosPaul A. Rabidoux
    • Toshiharu FurukawaMark C. HakeySteven J. HolmesDavid V. HorakJames S. NakosPaul A. Rabidoux
    • H01L2144
    • H01L21/76897H01L21/28123H01L21/823842H01L29/66575
    • Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.