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51. 发明授权

US06501117B1 Static self-refreshing DRAM structure and operating mode 失效
标题翻译：静态自刷新DRAM结构和工作模式
公开(公告)号：US06501117B1
公开(公告)日：2002-12-31
申请号：US10007846
申请日：2001-11-05
申请人： Carl J. Radens , Gary B. Bronner , Ramachandra Divakaruni , Jack A. Mandelman
发明人： Carl J. Radens , Gary B. Bronner , Ramachandra Divakaruni , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/11 , G11C11/404 , H01L27/10841 , H01L27/10864 , H01L27/10867 , H01L29/945
摘要： A DRAM cell storage capacitor is formed above the bottom of a deep trench (DT) below an FET transistor. The DT has upper, central and lower portions with sidewalls. A capacitor plate electrode, surrounding the lower DT portion that is doped with a first dopant type, is separated by an interface from a well region surrounding the upper and central portions of the DT that are doped with an opposite dopant type. A source/drain region formed at the top of the cell is doped with the first dopant type. A node dielectric layer that covers the sidewalls and bottom of the lower and central portions of the DT is filled with a node electrode of the capacitor, doped with the first dopant type, fills the space inside the node dielectric layer in the lower part of the DT. Above a recessed node dielectric layer a strap region space is filled with a buried-strap conductor. An oxide (TTO) layer is formed over the node electrode and the buried-strap in the DT. A peripheral gate oxide layer, which coats sidewalls of the DT above the TTO, defines a space which is filled with the FET gate electrode. An outdiffusion region, doped with the first dopant type, is formed in the well region near the buried-strap. The cell has a first state and an opposite state of operation. A punch-through device, formed in the well between the outdiffusion region and the interface, provides a self-refreshing punchthrough current in the cell between the well and the plate in the first state of cell operation. A reverse bias junction leakage current occurs in the cell between the buried-strap and the P-well to refresh the opposite state of cell operation.
摘要翻译：在FET晶体管下方的深沟槽（DT）的底部形成DRAM单元存储电容器。 DT具有具有侧壁的上部，中部和下部。围绕掺杂有第一掺杂剂类型的下部DT部分的电容器平板电极通过界面与围绕掺杂有相反掺杂剂类型的DT的上部和中部的阱区隔开。形成在电池顶部的源极/漏极区掺杂有第一掺杂剂类型。覆盖DT的下部和中心部分的侧壁和底部的节点电介质层填充有掺杂有第一掺杂剂类型的电容器的节点电极，填充第一掺杂剂类型的下部的节点电介质层内部的空间 DT。在凹陷节点电介质层上方，带区域空间填充有埋地导体。在DT上的节点电极和掩埋带上形成氧化物（TTO）层。在TTO上方覆盖DT的侧壁的外围栅极氧化物层限定了用FET栅电极填充的空间。在掩埋带附近的阱区中形成掺杂有第一掺杂剂类型的扩散区。电池具有第一状态和相反的操作状态。形成在扩散区域和界面之间的井中的穿通装置在电池操作的第一状态下在孔和板之间的电池单元中提供自刷新穿透电流。在埋层和P阱之间的电池中产生反向偏置结漏电流，以刷新电池操作的相反状态。

52. 发明授权

US06437388B1 Compact trench capacitor memory cell with body contact 失效
标题翻译：紧凑型沟槽电容器记忆体与身体接触
公开(公告)号：US06437388B1
公开(公告)日：2002-08-20
申请号：US09866278
申请日：2001-05-25
申请人： Carl J. Radens , Ulrike Gruening , Jack A. Mandelman
发明人： Carl J. Radens , Ulrike Gruening , Jack A. Mandelman
IPC分类号： H01L27108
CPC分类号： H01L27/10864 , H01L27/0218 , H01L27/10841 , H01L27/10876 , H01L27/10888 , H01L29/945
摘要： A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.
摘要翻译：半导体器件包括至少两个有效区域，每个有源区域围绕衬底中相应的沟槽。沟槽中的每一个都包括位于沟槽下部的电容器和沟槽上部的栅极。在上部的沟槽附近形成垂直晶体管，用于对电容器进行充电和放电。在所述至少两个活动区域之间形成身体接触。身体接触件连接到至少两个有源区域和衬底的扩散阱，以防止垂直晶体管中的浮体效应。

53. 发明授权

US06399447B1 Method of producing dynamic random access memory (DRAM) cell with folded bitline vertical transistor 失效
标题翻译：具有折叠位线垂直晶体管的动态随机存取存储器（DRAM）单元的制造方法
公开(公告)号：US06399447B1
公开(公告)日：2002-06-04
申请号：US09619671
申请日：2000-07-19
申请人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl J. Radens
发明人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21336
CPC分类号： H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A semiconductor device and a method for forming the semiconductor device, include forming a mandrel, forming spacer wordline conductors on sidewalls of the mandrel, separating, by using a trim mask, adjacent spacer wordline conductors, and providing a contact area to contact alternating ones of pairs of the spacer wordline conductors.
摘要翻译：半导体器件和用于形成半导体器件的方法包括形成心轴，在心轴的侧壁上形成间隔物字线导体，通过使用修剪掩模分离相邻间隔物字线导体，并提供接触区域以接触交替的一对间隔字线导线。

54. 发明授权

US06284593B1 Method for shallow trench isolated, contacted well, vertical MOSFET DRAM 失效
标题翻译：浅沟槽隔离方法，接触良好，垂直MOSFET DRAM
公开(公告)号：US06284593B1
公开(公告)日：2001-09-04
申请号：US09705652
申请日：2000-11-03
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10867
摘要： A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects is provided.
摘要翻译：提供了形成混合存储器单元的过程，该混合存储器单元在约1.5V的Vblh的工作电压下可扩展到约60nm的最小特征尺寸F，并且基本上没有浮动阱效应。

55. 发明授权

US06236077B1 Trench electrode with intermediate conductive barrier layer 失效
标题翻译：带中间导电阻挡层的沟槽电极
公开(公告)号：US06236077B1
公开(公告)日：2001-05-22
申请号：US09295136
申请日：1999-04-20
申请人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
发明人： Jeffrey P. Gambino , Rajarao Jammy , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10867 , H01L27/10861 , H01L29/66181 , H01L29/945
摘要： Reduced scale trench capacitor structures of improved reliability and decreased series resistance are enabled by the creation and use of conductive barrier layers at intermediate points in the trench electrode structure. The conductive barrier layer is preferably either an intrinsically conductive compound barrier or a quantum conductive barrier. The capacitor structures are preferably characterized by a lower electrode region of very high dopant concentration.
摘要翻译：通过在沟槽电极结构的中间点处产生和使用导电阻挡层，可实现提高可靠性和降低串联电阻的缩小沟槽电容器结构。导电阻挡层优选为本征导电化合物屏障或量子导电屏障。电容器结构的特征在于具有非常高掺杂剂浓度的下电极区域。

56. 发明申请

US20090047756A1 DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR 失效
标题翻译：双端口增益单元与侧面和顶部读取晶体管
公开(公告)号：US20090047756A1
公开(公告)日：2009-02-19
申请号：US12254960
申请日：2008-10-21
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L21/84 , H01L21/8242
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

57. 发明授权

US07459743B2 Dual port gain cell with side and top gated read transistor 有权
标题翻译：双端口增益单元，具有侧和顶栅控读取晶体管
公开(公告)号：US07459743B2
公开(公告)日：2008-12-02
申请号：US11161962
申请日：2005-08-24
申请人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
发明人： Jack A. Mandelman , Kangguo Cheng , Ramachandra Divakaruni , Carl J. Radens , Geng Wang
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译：使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。各种增益单元布局在本领域中是已知的。本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。

58. 发明授权

US06806534B2 Damascene method for improved MOS transistor 失效
标题翻译：改进MOS晶体管的镶嵌方法
公开(公告)号：US06806534B2
公开(公告)日：2004-10-19
申请号：US10342423
申请日：2003-01-14
申请人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

59. 发明授权

US06693041B2 Self-aligned STI for narrow trenches 失效
标题翻译：用于窄沟槽的自对准STI
公开(公告)号：US06693041B2
公开(公告)日：2004-02-17
申请号：US09885790
申请日：2001-06-20
申请人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21311
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
摘要翻译：通过蚀刻衬底中的多个垂直深沟槽并用氧化阻挡层涂覆沟槽，形成用于存储单元阵列的自对准浅沟槽隔离区。氧化阻挡层凹陷在沟槽的部分中以暴露沟槽中的衬底的部分。衬底的暴露部分通过氧化合并成热氧化物区域，以形成隔离衬底材料的相邻部分的自对准浅沟槽隔离结构。合并的氧化物区域是自对准的，因为它们在合成时自动对准深沟槽的边缘，以在IC制造期间限定存储单元阵列内的隔离区域的位置。瞬时自对准浅沟槽隔离结构避免了需要隔离掩模以在单个衬底上的相邻有效区域行内分离或隔离多个沟槽。

60. 发明授权

US06541815B1 High-density dual-cell flash memory structure 失效
标题翻译：高密度双单元闪存结构
公开(公告)号：US06541815B1
公开(公告)日：2003-04-01
申请号：US09974968
申请日：2001-10-11
申请人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
发明人： Jack A. Mandelman , Louis L. Hsu , Chung H. Lam , Carl J. Radens
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/7885
摘要： A 2F2 flash memory cell structure and a method of fabricating the same are provided. The 2F2 flash memory cell structure includes a Si-containing substrate having a plurality of trenches formed therein. Each trench has sidewalls that extend to a bottom wall, a length and individual segments that include two memory cell elements per segment. Each memory cell element comprises (i) a floating gate region having L-shaped gates formed on a portion of each trench sidewall; (ii) a program line overlapping one side of the L-shaped gates present at the bottom wall of each trench and extending along the entire length of the plurality of trenches; and (iii) a control gate region overlying the floating gate region. The control gate region includes gates formed on portions of the sidewalls of the trenches that are coupled to the floating gate regions. The memory cell structure further includes bitline diffusion regions formed in the Si-containing semiconductor substrate abutting each trench segment; and wordlines that lay orthogonal to the trenches. The wordlines are in contact with a top surface of each control gate region.
摘要翻译：提供了一种2F2闪存单元结构及其制造方法。 2F2闪存单元结构包括其中形成有多个沟槽的含Si衬底。每个沟槽具有延伸到底壁，长度和包括每个段的两个存储单元元件的单独段的侧壁。每个存储单元元件包括（i）具有形成在每个沟槽侧壁的一部分上的L形栅极的浮栅区域; （ii）重叠在每个沟槽的底壁处的L形门的一侧并沿多个沟槽的整个长度延伸的程序线; 和（iii）覆盖浮栅区域的控制栅极区域。控制栅极区域包括形成在沟槽的侧壁的与浮动栅极区域耦合的部分上的栅极。所述存储单元结构还包括形成在所述含Si半导体衬底中的位线邻接每个沟槽段的位线扩散区; 和与沟槽正交的字线。字线与每个控制栅极区域的顶表面接触。

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