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51. 发明申请

US20060237767A1 Semiconductor device with double barrier film 失效
公开(公告)号：US20060237767A1
公开(公告)日：2006-10-26
申请号：US11447947
申请日：2006-06-07
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/76 , H01L21/82
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

52. 发明申请

US20060202275A1 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same 失效
公开(公告)号：US20060202275A1
公开(公告)日：2006-09-14
申请号：US11434059
申请日：2006-05-16
申请人： Masayuki Ichige , Kikuko Sugimae , Riichiro Shirota
发明人： Masayuki Ichige , Kikuko Sugimae , Riichiro Shirota
IPC分类号： H01L29/76
CPC分类号： H01L27/11526 , H01L21/823842 , H01L21/82385 , H01L27/105 , H01L27/11529 , H01L27/11546
摘要： A semiconductor memory device provided with a memory cell region having first gate electrodes and a peripheral circuit region having second gate electrodes includes first gate electrodes arranged a first distance apart from each other on a semiconductor substrate, second gate electrodes arranged a second distance, which is larger than the first distance, apart from each other on the semiconductor substrate, first diffusion layers formed in the semiconductor substrate, the first diffusion layers sandwiching the first gate electrodes, second diffusion layers formed in the semiconductor substrate, the second diffusion layers sandwiching the second gate electrodes, a first insulating film formed on the first diffusion layer, second insulating films formed on the side surfaces of the second gate electrodes, first silicide films formed on the first gate electrodes, second silicide films formed on the second gate electrodes, and third silicide films formed on the second diffusion layers.

53. 发明授权

US07082055B2 Semiconductor integrated circuit device 失效
公开(公告)号：US07082055B2
公开(公告)日：2006-07-25
申请号：US11108634
申请日：2005-04-19
申请人： Masayuki Ichige , Riichiro Shirota , Kikuko Sugimae
发明人： Masayuki Ichige , Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0433 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.

54. 发明申请

US20060071293A1 Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same 失效
公开(公告)号：US20060071293A1
公开(公告)日：2006-04-06
申请号：US11283742
申请日：2005-11-22
申请人： Masayuki Ichige , Riichiro Shirota , Yuji Takeuchi , Kikuko Sugimae
发明人： Masayuki Ichige , Riichiro Shirota , Yuji Takeuchi , Kikuko Sugimae
IPC分类号： H01L29/00
CPC分类号： H01L27/11526 , H01L27/11 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11529 , H01L27/11531 , H01L27/11541 , H01L27/11543
摘要： An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed therebetween. A second conductive layer is formed on the first conductive layer to extend into the element isolating region. A surface of that section of the second conductive layer which is positioned within the element isolating region is exposed, and a third conductive layer is formed on the second conductive layer with a second insulating film interposed therebetween. Further, a contact is electrically connected to an exposed surface of the second conductive layer.

55. 发明申请

US20060065913A1 Semiconductor device with double barrier film 失效
标题翻译：具有双阻挡膜的半导体器件
公开(公告)号：US20060065913A1
公开(公告)日：2006-03-30
申请号：US11001223
申请日：2004-12-02
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L21/82 , H01L29/76
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

56. 发明申请

US20050281087A1 Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050281087A1
公开(公告)日：2005-12-22
申请号：US11211633
申请日：2005-08-26
申请人： Riichiro Shirota , Kikuko Sugimae
发明人： Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04 , G11C16/02 , G11C16/06 , H01L21/8234 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L31/109
CPC分类号： H01L27/11526 , G11C16/0433 , H01L27/105 , H01L27/11521 , H01L27/11529 , H01L27/11558
摘要： A memory cell has a selection transistor constituted of an MOS transistor having a gate electrode and a cell transistor constituted of an MOS transistor having the same polarity as the selection transistor, in such a configuration that these two transistors are connected in series. A bit line is connected to a drain region of the selection transistor and a word line is connected to the gate electrode thereof. A gate electrode of the cell transistor is not electrically connected anywhere so as to be in a floating potential state, while a drain region thereof is connected to a source region of the selection transistor. A source line is connected to a source region of the cell transistor.
摘要翻译：存储单元具有由具有栅电极的MOS晶体管和由与选择晶体管具有相同极性的MOS晶体管构成的单元晶体管构成的选择晶体管，其结构是这两个晶体管串联连接。位线连接到选择晶体管的漏极区域，并且字线连接到其栅电极。单元晶体管的栅极电极不会在任何地方电连接，以便处于浮置电位状态，而其漏极区域连接到选择晶体管的源极区域。源极线连接到单元晶体管的源极区域。

57. 发明申请

US20050224894A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050224894A1
公开(公告)日：2005-10-13
申请号：US11108634
申请日：2005-04-19
申请人： Masayuki Ichige , Riichiro Shirota , Kikuko Sugimae
发明人： Masayuki Ichige , Riichiro Shirota , Kikuko Sugimae
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/94
CPC分类号： H01L27/11521 , G11C16/04 , G11C16/0433 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A semiconductor integrated circuit device includes a semiconductor substrate, an element isolation region, a first interconnection, a second interconnection, and a memory cell unit connected between a corresponding one of the first interconnection and a second interconnection. The memory cell unit includes two selection transistors and memory cell transistors of not larger than two. The memory cell transistors are connected between the two selection transistors. The memory cell transistor has a charge storage layer whose side surface lies in the same plane or in substantially the same plane as the side surface of the element isolation regions.
摘要翻译：半导体集成电路器件包括半导体衬底，元件隔离区，第一互连，第二互连和连接在第一互连和第二互连中的相应一个之间的存储单元单元。存储单元单元包括不大于2的选择晶体管和存储单元晶体管。存储单元晶体管连接在两个选择晶体管之间。存储单元晶体管具有电荷存储层，该电荷存储层的侧表面位于与元件隔离区的侧表面相同的平面或基本上相同的平面中。

58. 发明申请

US20050073001A1 Nonvolatile semiconductor memory and fabrication method therefor 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20050073001A1
公开(公告)日：2005-04-07
申请号：US10892445
申请日：2004-07-16
申请人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Fumitaka Arai , Kikuko Sugimae
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L29/4236 , H01L29/7881
摘要： This nonvolatile semiconductor memory includes: a first and a second memory cell column having memory cell transistors connected in series with a floating gate and a first and a second control gate located at both sides of that floating gate; a first select-gate transistor connected between the first memory cell column and a bit line; a second select-gate transistor connected between the second memory cell column and the bit line; and a third select gate transistor connected between the first memory cell column and a source line and also between the second memory cell column and the source line, respectively.
摘要翻译：该非易失性半导体存储器包括：具有与浮动栅极串联连接的存储单元晶体管的第一和第二存储单元列以及位于该浮置栅极两侧的第一和第二控制栅极; 连接在第一存储单元列和位线之间的第一选择栅晶体管; 连接在第二存储单元列和位线之间的第二选择栅晶体管; 以及分别连接在第一存储单元列和源极线之间以及第二存储单元列和源极线之间的第三选择栅极晶体管。

59. 发明授权

US06667507B2 Flash memory having memory section and peripheral circuit section 失效
标题翻译：具有存储器部分和外围电路部分的闪存
公开(公告)号：US06667507B2
公开(公告)日：2003-12-23
申请号：US09899155
申请日：2001-07-06
申请人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
发明人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译：半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

60. 发明授权

US08817523B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08817523B2
公开(公告)日：2014-08-26
申请号：US13601826
申请日：2012-08-31
申请人： Kikuko Sugimae
发明人： Kikuko Sugimae
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0011 , G11C13/0033 , G11C13/004 , G11C2213/71 , G11C2213/73
摘要： A non-volatile semiconductor memory device includes a memory cell array including a first wire, a second wire crossing the first wire, and a memory cell connected to both the wires at a crossing portion of the first wire and the second wire, the memory cell including a variable resistance element storing data in a non-volatile manner by a resistance value, and a control circuit setting the variable resistance element in first or second resistance state by application of first or second voltage to the memory cell and reading data from the memory cell by application of third voltage to the memory cell. The control circuit applies to the memory cell at predetermined timing weak write voltage causing the variable resistance element to be held in the first resistance state and the second resistance state.
摘要翻译：非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括第一线，与第一线交叉的第二线，以及与第一线和第二线的交叉部分处的两条线连接的存储单元，存储单元包括通过电阻值以非易失性方式存储数据的可变电阻元件以及通过向存储器单元施加第一或第二电压并从存储器读取数据来将可变电阻元件设置在第一或第二电阻状态的控制电路通过将第三电压施加到存储器单元。控制电路以预定的定时将弱写入电压施加到存储单元，使可变电阻元件保持在第一电阻状态和第二电阻状态。

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