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1. 发明授权

US08400812B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08400812B2
公开(公告)日：2013-03-19
申请号：US13231510
申请日：2011-09-13
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Mitsuhiro Noguchi
IPC分类号： G11C5/06 , G11C5/02 , G11C16/04
CPC分类号： G11C16/0483 , G11C5/063 , G11C8/14 , H01L27/0207 , H01L27/088 , H01L27/11519 , H01L27/11529
摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列和外围电路。存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。外围电路具有晶体管组。晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

2. 发明授权

US07939908B2 High-voltage transistor having shielding gate 有权
标题翻译：具有屏蔽门的高电压晶体管
公开(公告)号：US07939908B2
公开(公告)日：2011-05-10
申请号：US11510584
申请日：2006-08-28
申请人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
发明人： Hiroyuki Kutsukake , Kikuko Sugimae , Takeshi Kamigaichi
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译：半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。

3. 发明申请

US20090154214A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20090154214A1
公开(公告)日：2009-06-18
申请号：US12370638
申请日：2009-02-13
申请人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
发明人： Kikuko Sugimae , Satoshi Tanaka , Koji Hashimoto , Masayuki Ichige
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/063 , G11C16/0408 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.
摘要翻译：用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。半导体存储器包括：多个有源区域AAi，AAi，...。。。，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。。。沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。。。被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

4. 发明授权

US07504294B2 Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：制造电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US07504294B2
公开(公告)日：2009-03-17
申请号：US10881180
申请日：2004-07-01
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

5. 发明申请

US20080251881A1 SEMICONDUCTOR DEVICE WITH DOUBLE BARRIER FILM 失效
标题翻译：具有双屏障膜的半导体器件
公开(公告)号：US20080251881A1
公开(公告)日：2008-10-16
申请号：US12143597
申请日：2008-06-20
申请人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
发明人： Makoto Sakuma , Yasuhiko Matsunaga , Fumitaka Arai , Kikuko Sugimae
IPC分类号： H01L29/00
CPC分类号： H01L27/115 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.
摘要翻译：一种半导体器件，包括第一绝缘层，第二绝缘层，第一阻挡膜，第二阻挡膜，扩散层。该装置还包括上接触孔，下接触孔和接触塞。上接触孔穿透第二绝缘层，并且在第二阻挡膜中具有底部。底部的宽度大于在与沟槽宽度方向交叉的方向上测量的在第一绝缘层中形成的沟槽。下接触孔穿过第一绝缘层和第一阻挡膜，经由沟槽与第一接触孔连通并设置在扩散层上。下接触孔的上部具有与沟槽相同的宽度。接触塞设置在上接触孔和下接触孔中。

6. 发明授权

US07417281B2 Semiconductor device with a selection gate and a peripheral gate 有权
标题翻译：具有选择栅极和外围栅极的半导体器件
公开(公告)号：US07417281B2
公开(公告)日：2008-08-26
申请号：US11733488
申请日：2007-04-10
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L29/94
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

7. 发明授权

US07369439B2 Semiconductor integrated circuit device having nonvolatile semiconductor memory and programming method thereof 失效
标题翻译：具有非易失性半导体存储器的半导体集成电路器件及其编程方法
公开(公告)号：US07369439B2
公开(公告)日：2008-05-06
申请号：US11397725
申请日：2006-04-05
申请人： Takeshi Kamigaichi , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Kikuko Sugimae
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C2216/14 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.
摘要翻译：半导体集成电路器件包括具有以矩阵形式布置的多个存储单元晶体管的存储单元阵列。该装置还包括布置在存储单元阵列的外围区域中的高压电路区域，并且包括具有电流路径的第一高压晶体管，该电流路径一端连接到选定的控制栅极和第二高压晶体管具有电流路径，其一端连接到与所选择的控制栅极相邻的第一未选择的控制栅极，并且被配置为通过使用在所选择的控制栅极之间产生的第一电容耦合来提高施加到所选择的控制栅极的编程电压以及通过施加近似等于使存储单元晶体管的电流路径导通到第一未选择的控制栅极的电压的中间电压而使第一未选择的控制栅极。

8. 发明授权

US07361951B2 Flash memory having memory section and peripheral circuit section 失效
标题翻译：具有存储器部分和外围电路部分的闪存
公开(公告)号：US07361951B2
公开(公告)日：2008-04-22
申请号：US11259142
申请日：2005-10-27
申请人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
发明人： Riichiro Shirota , Kikuko Sugimae , Masayuki Ichige , Atsuhiro Sato , Hiroaki Hazama
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译：半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。

9. 发明申请

US20070148973A1 Fabrication of semiconductor device for flash memory with increased select gate width 有权
标题翻译：具有增加选择栅极宽度的闪存半导体器件制造
公开(公告)号：US20070148973A1
公开(公告)日：2007-06-28
申请号：US11319895
申请日：2005-12-28
申请人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
发明人： Masaaki Higashitani , Tuan Pham , Masayuki Ichige , Koji Hashimoto , Satoshi Tanaka , Kikuko Sugimae
IPC分类号： H01L21/302 , B44C1/22 , H01L21/461
CPC分类号： H01L21/28123 , H01L21/32139 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.
摘要翻译：使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以产生类似的最终结构。

10. 发明申请

US20060239069A1 Semiconductor integrated circuit device having nonvolatile semiconductor memory and programming method thereof 失效
标题翻译：具有非易失性半导体存储器的半导体集成电路器件及其编程方法
公开(公告)号：US20060239069A1
公开(公告)日：2006-10-26
申请号：US11397725
申请日：2006-04-05
申请人： Takeshi Kamigaichi , Kikuko Sugimae
发明人： Takeshi Kamigaichi , Kikuko Sugimae
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0483 , G11C2216/14 , H01L27/105 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes a memory cell array having a plurality of memory cell transistors arranged in a matrix form. The device further includes a high-voltage circuit area arranged in a peripheral area of the memory cell array and including a first high-voltage transistor having a current path which is connected at one end to a selected control gate and a second high-voltage transistor having a current path which is connected at one end to a first non-selected control gate adjacent to the selected control gate and configured to raise voltage applied to the selected control gate to program voltage by use of first capacitive coupling caused between the selected control gate and the first non-selected control gate by applying intermediate voltage approximately equal to voltage which makes the current path of the memory cell transistor conductive to the first non-selected control gate.
摘要翻译：半导体集成电路器件包括具有以矩阵形式布置的多个存储单元晶体管的存储单元阵列。该装置还包括布置在存储单元阵列的外围区域中的高压电路区域，并且包括具有电流路径的第一高压晶体管，该电流路径一端连接到选定的控制栅极和第二高压晶体管具有电流路径，其一端连接到与所选择的控制栅极相邻的第一未选择的控制栅极，并且被配置为通过使用在所选择的控制栅极之间产生的第一电容耦合来提高施加到所选择的控制栅极的编程电压以及通过施加近似等于使存储单元晶体管的电流路径导通到第一未选择的控制栅极的电压的中间电压而使第一未选择的控制栅极。

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