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    • 54. 发明授权
    • Ferroelectric memory configuration having successively connected ferroelectric capacitor coupling to the gate of a read transistor and different bias voltages applied in read/write/erase
    • 铁电存储器配置具有连续的铁电电容器耦合到读取晶体管的栅极和在读/写/擦除中施加的不同偏置电压
    • US06967859B2
    • 2005-11-22
    • US10626722
    • 2003-07-25
    • Yoshihisa KatoYasuhiro Shimada
    • Yoshihisa KatoYasuhiro Shimada
    • G11C11/22
    • G11C11/22G11C11/223
    • A semiconductor memory of this invention contains a memory cell block including a plurality of ferroelectric capacitors successively connected to one another along a bit line direction each for storing a data in accordance with displacement of polarization of a ferroelectric film thereof, and a reading transistor whose gate is connected to one end of the successively connected plural ferroelectric capacitors for reading a data by detecting the displacement of the polarization of the ferroelectric film of a ferroelectric capacitor selected from the plural ferroelectric capacitors. A set line is connected to the other end of the successively connected plural ferroelectric capacitors. A bit line is connected to the drain of the reading transistor at one end thereof. A reset line is connected to the source of the reading transistor at one end thereof. A plurality of word lines respectively corresponding to the plural ferroelectric capacitors are provided perpendicularly to the bit line, so as to select a ferroelectric capacitor from the plural ferroelectric capacitors for data write or data read.
    • 本发明的半导体存储器包括存储单元块,该存储单元块包括沿着位线方向依次连接的多个强电介质电容器,每个强电介质电容器用于根据其铁电体膜的极化位移存储数据;以及读取晶体管,其栅极 通过检测从多个强电介质电容器中选出的铁电体电容器的铁电体膜的极化位移来连接到连续连接的多个铁电电容器的一端,用于读取数据。 设定线连接到连续连接的多个铁电电容器的另一端。 位线在其一端连接到读取晶体管的漏极。 复位线在其一端连接到读取晶体管的源极。 分别对应于多个强电介质电容器的多个字线垂直于位线设置,以从多个用于数据写入或数据读取的强电介质电容器中选择铁电电容器。