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51. 发明申请

US20080224123A1 Methods for nanowire alignment and deposition 有权
标题翻译：纳米线对准和沉积的方法
公开(公告)号：US20080224123A1
公开(公告)日：2008-09-18
申请号：US11979949
申请日：2007-11-09
申请人： Samuel Martin , Xiangfeng Duan , Katsumasa Fujii , James M. Hamilton , Hiroshi Iwata , Francisco Leon , Jeffrey Miller , Tetsu Negishi , Hiroshi Ohki , J. Wallace Parce , Cheri X.Y. Pereira , Paul John Schuele , Akihide Shibata , David P. Stumbo , Yasunobu Okada
发明人： Samuel Martin , Xiangfeng Duan , Katsumasa Fujii , James M. Hamilton , Hiroshi Iwata , Francisco Leon , Jeffrey Miller , Tetsu Negishi , Hiroshi Ohki , J. Wallace Parce , Cheri X.Y. Pereira , Paul John Schuele , Akihide Shibata , David P. Stumbo , Yasunobu Okada
IPC分类号： H01L31/00 , H01L21/326
CPC分类号： H01L29/0665 , B82B3/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L29/0673 , Y10S977/883
摘要： The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.
摘要翻译：本发明提供了用于纳米线对准和沉积的方法和系统。使用通电（例如，交流电场）来使纳米线与电极对准和关联。通过调节激励，纳米线耦合到电极，使得它们在随后的洗涤和干燥步骤期间保持在适当的位置。本发明还提供了将纳米线从一个衬底转移到另一个衬底以便制备各种器件衬底的方法。本发明还提供了用于监测和控制在特定电极对上沉积的纳米线的数量的方法，以及用于操纵溶液中的纳米线的方法。

52. 发明授权

US07372758B2 Semiconductor memory device, method for controlling the same, and mobile electronic device 有权
标题翻译：半导体存储器件，其控制方法和移动电子器件
公开(公告)号：US07372758B2
公开(公告)日：2008-05-13
申请号：US10529880
申请日：2003-10-02
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Kei Tokui , Masaru Nawaki
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Kei Tokui , Masaru Nawaki
IPC分类号： G11C7/00
CPC分类号： H01L21/28273 , G11C16/225 , H01L29/7887
摘要： A memory cell array employs a memory element as a memory cell. The memory element is constructed of a gate electrode formed via a gate insulation film on a semiconductor layer, a channel region arranged under the gate electrode, diffusion regions that are arranged on both sides of the channel region and have a conductive type opposite to that of the channel region, and memory function bodies that are arranged on both sides of the gate electrode and have a function to retain electric charges. When first and second power voltages VCC1 and VCC2 supplied from the outside are lower than a prescribed voltage, a rewrite command to a memory circuit 34 that includes the memory cell array is inhibited by a lockout circuit 33a. With this arrangement, there are provided a semiconductor storage device capable of achieving storage retainment of two bits or more per memory element and stable operation even if the device is miniaturized and preventing the occurrence of a malfunction of rewrite error and so on attributed to a reduction in the power voltage supplied from the outside and a control method therefor.
摘要翻译：存储单元阵列采用存储元件作为存储单元。存储元件由在半导体层上形成的栅极绝缘膜，配置在栅电极下方的沟道区域形成的栅极电极构成，扩散区域配置在沟道区域的两侧，具有与沟道区域和存储器功能体，其布置在栅电极的两侧并具有保持电荷的功能。当从外部提供的第一和第二电源电压VCC 1和VCC 2低于规定电压时，由锁存电路33a禁止包括存储单元阵列的存储电路34的重写命令。通过这种布置，提供了一种半导体存储装置，其能够实现每个存储元件的两位或更多的存储保持和稳定的操作，即使该装置小型化并且防止归因于减少的重写错误等的故障的发生在外部提供的电源电压及其控制方法中。

53. 发明申请

US20080042120A1 Integrated circuit device, manufacturing method thereof, and display device 有权
标题翻译：集成电路装置及其制造方法以及显示装置
公开(公告)号：US20080042120A1
公开(公告)日：2008-02-21
申请号：US11802706
申请日：2007-05-24
申请人： Akihide Shibata , Katsumasa Fujii , Yutaka Takafuji , Hiroshi Iwata
发明人： Akihide Shibata , Katsumasa Fujii , Yutaka Takafuji , Hiroshi Iwata
IPC分类号： H01L29/06 , H01L21/44 , H01L33/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/823807 , H01L27/092 , H01L27/15 , H01L29/0673 , H01L29/78654 , H01L29/78681 , H01L29/78684 , H01L29/78696 , Y10S977/762 , Y10S977/781 , Y10S977/789
摘要： An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types of nano wire element. With this, it is possible to dramatically improve a function of the integrated circuit device, as compared with an integrated circuit device including a substrate on which one type of nano wire element is provided.
摘要翻译：本发明的集成电路器件包括其上提供至少两种类型的纳米线元件的衬底。这些纳米线元件具有彼此不同的功能和材料。纳米线元件由具有与纳米线元件的类型不同的尺寸的纳米线构成。与包括其上提供有一种类型的纳米线元件的基板的集成电路器件相比，可以显着地提高集成电路器件的功能。

54. 发明授权

US07304340B2 Semiconductor storage elements, semiconductor device manufacturing methods therefor, portable electronic equipment and IC card 失效
标题翻译：半导体存储元件，半导体器件制造方法，便携式电子设备和IC卡
公开(公告)号：US07304340B2
公开(公告)日：2007-12-04
申请号：US10848323
申请日：2004-05-19
申请人： Takayuki Ogura , Hiroshi Iwata , Akihide Shibata
发明人： Takayuki Ogura , Hiroshi Iwata , Akihide Shibata
IPC分类号： H01L29/76
CPC分类号： B82Y10/00 , G11C16/0458 , G11C2216/06 , H01L21/28273 , H01L29/42332 , H01L29/7887
摘要： A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respect to an edge of the gate electrode in a gate length direction to improve efficiency of electric charge injection into the memory function body. A storage state in the memory function body is found by detecting a amount of current between the source/drain regions, which current changes depending on the amount of the electric charge retained in the charge retention portion.
摘要翻译：半导体存储元件在半导体衬底上形成的栅电极的相对侧上具有记忆功能体。源极/漏极区域的每个端部位于存储器功能体正下方的半导体衬底中，并且相对于栅电极的栅极长度方向的边缘偏移，以提高电荷注入存储器功能体的效率。通过检测源极/漏极区域之间的电流量来确定存储器功能体中的存储状态，该电流/电流区域中的电流根据电荷保留部分中保留的电荷量而变化。

55. 发明授权

US07187594B2 Semiconductor storage device, semiconductor device, manufacturing method of semiconductor storage device, and mobile electronic device 有权
标题翻译：半导体存储装置，半导体装置，半导体存储装置的制造方法以及移动电子装置
公开(公告)号：US07187594B2
公开(公告)日：2007-03-06
申请号：US10844563
申请日：2004-05-13
申请人： Akihide Shibata , Hiroshi Iwata
发明人： Akihide Shibata , Hiroshi Iwata
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C7/1012 , G11C7/18 , G11C16/04 , G11C16/28 , G11C2207/002 , H01L21/28273 , H01L29/7923
摘要： A volatile memory element and a nonvolatile memory element, each of which is constituted of a field effect transistor, are formed on a single semiconductor chip. The volatile memory element includes a body region, a gate electrode, and two diffusion layer regions, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to a gate electrode, in accordance with an amount of electric charge retained in the body region. The nonvolatile memory element includes diffusion layer regions, a gate electrode, and two memory function sections, and varies an amount of a current, flowing between the diffusion layer regions in applying a voltage to the gate electrode, in accordance with an amount of electric charge retained in the memory function sections. Thus, it is possible to form the volatile memory and the nonvolatile memory on a single chip with a simple process.
摘要翻译：在单个半导体芯片上形成由场效应晶体管构成的易失性存储元件和非易失性存储元件。易失性存储元件包括体区域，栅极电极和两个扩散层区域，并且根据电荷量改变在向栅电极施加电压的扩散层区域之间流动的电流量保留在身体区域。非易失性存储元件包括扩散层区域，栅极电极和两个存储器功能部分，并且根据电荷量改变在施加电压至栅电极的扩散层区域之间流动的电流量保留在记忆功能部分。因此，可以通过简单的处理在单个芯片上形成易失性存储器和非易失性存储器。

56. 发明授权

US07177188B2 Semiconductor memory device, display device, and portable electronic apparatus 有权
标题翻译：半导体存储器件，显示器件和便携式电子设备
公开(公告)号：US07177188B2
公开(公告)日：2007-02-13
申请号：US10775254
申请日：2004-02-11
申请人： Hiroshi Iwata , Akihide Shibata , Yoshifumi Yaoi , Yasuaki Iwase , Masaru Nawaki , Yoshinao Morikawa , Kenichi Tanaka
发明人： Hiroshi Iwata , Akihide Shibata , Yoshifumi Yaoi , Yasuaki Iwase , Masaru Nawaki , Yoshinao Morikawa , Kenichi Tanaka
IPC分类号： G11C16/00
CPC分类号： H01L21/28273 , G11C16/0408 , H01L21/28282 , H01L29/7923
摘要： A semiconductor memory device includes: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.
摘要翻译：半导体存储器件包括：存储单元，具有通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧的扩散区域，并具有相反的导电类型形成在栅电极的两侧并具有保持电荷的功能的存储器功能单元; 以及放大器，存储单元和放大器彼此连接，使得存储单元的输出被输入到放大器。

57. 发明申请

US20060208312A1 Semiconductor storage device and manufacturing method therefor, semiconductor device, portable electronic equipment and IC card 有权
标题翻译：半导体存储器件及其制造方法，半导体器件，便携式电子设备和IC卡
公开(公告)号：US20060208312A1
公开(公告)日：2006-09-21
申请号：US11414226
申请日：2006-05-01
申请人： Hiroshi Iwata , Takayuki Ogura , Akihide Shibata , Kouichirou Adachi
发明人： Hiroshi Iwata , Takayuki Ogura , Akihide Shibata , Kouichirou Adachi
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , G11C16/0491 , H01L21/28282 , H01L21/28291 , H01L21/76831 , H01L21/76897 , H01L27/115 , H01L29/42332 , H01L29/6656 , H01L29/66833 , H01L29/7887 , H01L29/7923 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor storage device includes a field effect transistor which has a gate insulator, a gate electrode and a pair of source/drain diffusion regions on a semiconductor substrate. The device also includes a coating film made of a dielectric having a function of storing electric charge and formed on the substrate in such a manner as to cover an upper surface and side surfaces of the gate electrode. The device further includes an interlayer insulator formed on and in contact with the coating film. The device still further includes contact members which extend vertically through the interlayer insulator and the coating film on the source/drain diffusion regions and which are electrically connected to the source/drain diffusion regions, respectively. The coating film and the interlayer insulator are made of materials which are selectively etchable to each other. Thus, the issues of overerase and read failures due to the overerase can be solved, and the device reliability can be enhanced.
摘要翻译：半导体存储装置包括在半导体衬底上具有栅极绝缘体，栅极电极和一对源极/漏极扩散区域的场效应晶体管。该装置还包括由电介质构成的涂膜，其具有存储电荷的功能，并以覆盖栅电极的上表面和侧表面的方式形成在基板上。该装置还包括形成在涂膜上并与涂膜接触的层间绝缘体。该装置还包括分别垂直延伸通过层间绝缘体和源极/漏极扩散区上的涂膜并且分别与源/漏扩散区电连接的接触构件。涂膜和层间绝缘体由可相互选择性地蚀刻的材料制成。因此，可以解决由于过度过热导致的过度读取和读取故障的问题，并且可以提高器件的可靠性。

58. 发明申请

US20060197142A1 Semiconductor storage device, manufacturing method therefor, and portable electronic equipment 有权
公开(公告)号：US20060197142A1
公开(公告)日：2006-09-07
申请号：US11366479
申请日：2006-03-03
申请人： Hiroshi Iwata , Akihide Shibata , Masayuki Nakano
发明人： Hiroshi Iwata , Akihide Shibata , Masayuki Nakano
IPC分类号： H01L29/788
CPC分类号： G11C16/0475 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/792 , H01L29/7923
摘要： A semiconductor storage device has a semiconductor layer having a first conductivity type region and two second conductivity type regions separated from each other by the first conductivity type region, a memory function body formed on a surface of the semiconductor layer, and a gate electrode. The memory function body has a charge storage insulator and a charge retention insulator positioned between the charge storage insulator and the semiconductor layer, and doubles as a gate insulating film. The charge retention insulator contains such impurity atoms (phosphorus) as would cause an intrinsic semiconductor to be of the second conductivity type.

59. 发明授权

US07050337B2 Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus 失效
标题翻译：半导体存储装置的写入控制方法和写入控制系统以及便携式电子设备
公开(公告)号：US07050337B2
公开(公告)日：2006-05-23
申请号：US10848082
申请日：2004-05-19
申请人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C7/00
CPC分类号： G11C16/24
摘要： A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.
摘要翻译：一种向非易失性半导体存储装置提供高速写入的写入控制系统，包括：（a）多个存储元件，每个存储元件具有：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极两侧的具有保持电荷功能的存储器功能部件，（b）包括页缓冲电路的存储器阵列，（c）CPU控制对存储器阵列的写入。 CPU用第一个数据字节加载页面缓冲电路的第一个平面，并用第一个平面中存储的数据的第一个字节进行写入。此外，CPU将第二字节的数据写入第二平面，并且将已经存储在第一平面中的数据的第一字节写入存储器阵列中，将已经存储在第二平面中的数据的第二字节写入。

60. 发明授权

US07050331B2 Semiconductor memory device and portable electronic apparatus 失效
标题翻译：半导体存储器件和便携式电子设备
公开(公告)号：US07050331B2
公开(公告)日：2006-05-23
申请号：US10851709
申请日：2004-05-20
申请人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
发明人： Nobuaki Matsuoka , Masaru Nawaki , Yoshinao Morikawa , Hiroshi Iwata , Akihide Shibata
IPC分类号： G11C16/04
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/10 , G11C16/16 , H01L21/28282 , H01L29/7923
摘要： The present invention provides a semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, a user interface circuit including a command queue having a logic circuit for accepting commands issued by an external user and generating a program memory address, and an array control circuit having a microcontroller and a program memory for storing therein an execution code, and executing an operation on the memory cell array, wherein the memory cell includes a gate electrode formed over a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional elements formed on both sides of the gate electrode and having the function of retaining charges.
摘要翻译：本发明提供了一种半导体存储器件，包括其中布置有多个存储器单元的存储单元阵列，用户接口电路包括具有用于接受由外部用户发出的命令并产生程序存储器地址的逻辑电路的命令队列，以及阵列控制电路，具有微控制器和程序存储器，用于在其中存储执行代码，并对存储单元阵列执行操作，其中存储单元包括通过栅极绝缘膜形成在半导体层上的栅电极，设置在栅极电极下方的扩散区域，设置在沟道区域的两侧并具有与沟道区域相反的导电类型的扩散区域，以及形成在栅电极两侧并具有保持电荷功能的存储功能元件。

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