专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20140306344A1 WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING WIRING STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：布线结构，包括布线结构的半导体器件，以及制造半导体器件的方法
公开(公告)号：US20140306344A1
公开(公告)日：2014-10-16
申请号：US14313026
申请日：2014-06-24
申请人： Shigetoshi Sugawa , Akinobu Teramoto , Rihito Kuroda , Gu Xun
发明人： Shigetoshi Sugawa , Akinobu Teramoto , Rihito Kuroda , Gu Xun
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/02063 , H01L21/0212 , H01L21/02126 , H01L21/02167 , H01L21/02211 , H01L21/02274 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L21/76808 , H01L21/76831 , H01L21/76843 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components.
摘要翻译：设有布线结构。布线结构具有包括金属布线的镶嵌布线结构。金属布线与含有硅（Si），碳（C）和氧（O）和氮（N）中的至少一种的阻挡膜（SiC（O，N）膜）的上表面直接接触，作为组成部分。

52. 发明申请

US20130320477A1 METHOD OF ETCHING OF SOI SUBSTRATE, AND BACK-ILLUMINATED PHOTOELECTRIC CONVERSION MODULE ON SOI SUBSTRATE AND PROCESS OF MANUFACTURE THEREOF 有权
标题翻译： SOI衬底的蚀刻方法和SOI衬底上的后照明光电转换模块及其制造方法
公开(公告)号：US20130320477A1
公开(公告)日：2013-12-05
申请号：US13883828
申请日：2011-10-28
申请人： Tadahiro Ohmi , Tomotsugu Ohashi , Kazuhiro Yoshikawa , Tatsuro Yoshida , Teppei Uchimura , Kazuki Soeda , Shigetoshi Sugawa
发明人： Tadahiro Ohmi , Tomotsugu Ohashi , Kazuhiro Yoshikawa , Tatsuro Yoshida , Teppei Uchimura , Kazuki Soeda , Shigetoshi Sugawa
IPC分类号： H01L31/0248 , H01L21/306
CPC分类号： H01L31/0248 , H01L21/30604 , H01L21/6708 , H01L27/1464 , H01L29/78603
摘要： A method of etching capable of rapidly and flatly performing wet etching on a Si substrate using fluonitric acid represented by HF(a)HNO3(b)H2O(c) (where the unit of a, b and c is wt % and a+b+c=100). The etching rate of an SiO2 layer with the highly concentrated fluonitric acid is significantly lowered by the appropriate selection of its composition as compared with the etching rate of the Si substrate, and etch the Si substrate until the SiO2 layer is exposed. In this way, it is possible to rapidly etch the Si substrate and significantly enhance the flatness of the etched surface.
摘要翻译：使用HF（a）HNO 3（b）H 2 O（c）（其中a，b和c的单位为wt％和a + b）表示的氟酸，在Si衬底上快速且平坦地进行湿蚀刻的方法 + c = 100）。与Si衬底的蚀刻速率相比，通过适当选择其组成，通过适当选择具有高浓度荧光酮的SiO 2层的蚀刻速率，并且蚀刻Si衬底直至暴露SiO 2层。以这种方式，可以快速蚀刻Si衬底并显着提高蚀刻表面的平坦度。

53. 发明授权

US08530947B2 Solid-state image sensor 有权
标题翻译：固态图像传感器
公开(公告)号：US08530947B2
公开(公告)日：2013-09-10
申请号：US13382878
申请日：2010-06-23
申请人： Yasushi Kondo , Hideki Tominaga , Kenji Takubo , Ryuta Hirose , Shigetoshi Sugawa , Hideki Mutoh
发明人： Yasushi Kondo , Hideki Tominaga , Kenji Takubo , Ryuta Hirose , Shigetoshi Sugawa , Hideki Mutoh
IPC分类号： H01L27/148
CPC分类号： H01L27/14603 , H01L27/14607 , H01L27/14609 , H01L27/1461
摘要： A floating diffusion region is formed at an edge of a light-receiving surface of an embedded photodiode, with a transfer gate electrode located therebetween. A first region, with radially extending portions centered on the FD region, and a second region, located to the outside of the first region, are created in the substantially sector-shaped light-receiving surface. A dopant whose conductivity type is the same as the signal charges to be collected in the first region are introduced, whereby an electric field for moving the signal charges from the radially extending sections towards the center is created due to a three-dimensional field effect. As a result, the charge-transfer time is reduced. Additionally, since a circuit element in the subsequent stage can be placed adjacent to the floating diffusion region, the parasitic capacitance of the floating diffusion region can be reduced and a highly sensitive element can be obtained.
摘要翻译：在嵌入式光电二极管的光接收表面的边缘处形成浮动扩散区，其中位于其间的传输栅电极。在大致扇形的光接收表面上形成有以FD区域为中心的径向延伸部分的第一区域和位于第一区域外部的第二区域。引入导电类型与要在第一区域中收集的信号电荷相同的掺杂剂，由此由于三维场效应，产生用于使信号从径向延伸部分向中心移动的电场。结果，电荷转移时间减少。此外，由于随后阶段的电路元件可以放置在与浮动扩散区域相邻的位置，所以可以减小浮动扩散区域的寄生电容，并且可以获得高灵敏度的元件。

54. 发明申请

US20110110052A1 MULTILAYER WIRING BOARD 有权
标题翻译：多层接线板
公开(公告)号：US20110110052A1
公开(公告)日：2011-05-12
申请号：US12995514
申请日：2009-05-22
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Hiroshi Imai , Akinobu Teramoto
IPC分类号： H05K1/18 , H05K1/00
CPC分类号： H05K1/0218 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2223/6688 , H01L2924/0002 , H01L2924/19032 , H01L2924/3011 , H05K1/025 , H05K1/0265 , H05K3/4652 , H05K2201/0191 , H05K2201/0352 , H05K2201/0715 , H05K2201/096 , H05K2201/09618 , H05K2201/09727 , H05K2201/09972 , H01L2924/00
摘要： A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.
摘要翻译：多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

55. 发明申请

US20110069358A1 SOLID-STATE IMAGING DEVICE 有权
公开(公告)号：US20110069358A1
公开(公告)日：2011-03-24
申请号：US12958817
申请日：2010-12-02
申请人： Tomoya Yoneda , Shigetoshi Sugawa , Toru Koizumi , Tetsunobu Kochi
发明人： Tomoya Yoneda , Shigetoshi Sugawa , Toru Koizumi , Tetsunobu Kochi
IPC分类号： H04N1/04
CPC分类号： H04N1/195 , H01L27/14603 , H01L27/14609 , H01L27/14623 , H01L27/14643
摘要： To control the potential distribution generated in a well at the time of amplification and reduce a shading in a solid-state imaging device of amplification type, the amplification type solid-state imaging device of the present invention comprises a plurality of picture elements each including photoelectric conversion elements formed in a second conductivity type common well inside a first conductivity type substrate, wherein a plurality of well contacts are disposed inside a picture element array area.

56. 发明授权

US07864384B2 Solid-state imaging device 有权
标题翻译：固态成像装置
公开(公告)号：US07864384B2
公开(公告)日：2011-01-04
申请号：US12264972
申请日：2008-11-05
申请人： Tomoya Yoneda , Shigetoshi Sugawa , Toru Koizumi , Tetsunobu Kochi
发明人： Tomoya Yoneda , Shigetoshi Sugawa , Toru Koizumi , Tetsunobu Kochi
IPC分类号： H04N1/04
CPC分类号： H04N1/195 , H01L27/14603 , H01L27/14609 , H01L27/14623 , H01L27/14643
摘要： To control the potential distribution generated in a well at the time of amplification and reduce a shading in a solid-state imaging device of amplification type, the amplification type solid-state imaging device of the present invention comprises a plurality of picture elements each including photoelectric conversion elements formed in a second conductivity type common well inside a first conductivity type substrate, wherein a plurality of well contacts are disposed inside a picture element array area.
摘要翻译：为了控制放大时在阱中产生的电位分布并减小放大型固态成像装置中的阴影，本发明的放大型固态成像装置包括多个图像元素，每个图像元素包括光电形成在第一导电型衬底内的第二导电类型共同阱中的转换元件，其中多个阱触点设置在像素阵列区域内。

57. 发明授权

US07812595B2 Electronic device identifying method 失效
标题翻译：电子设备识别方法
公开(公告)号：US07812595B2
公开(公告)日：2010-10-12
申请号：US12032998
申请日：2008-02-18
申请人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： G01R31/28
CPC分类号： H01L23/544 , G01R31/31718 , G11C2029/4402 , H01L21/76254 , H01L22/14 , H01L2223/5444 , H01L2924/0002 , Y10T29/49004 , H01L2924/00
摘要： There is provided a device identifying method for identifying an electronic device including therein an actual operation circuit and a test circuit having a plurality of test elements provided therein, where the actual operation circuit operates during an actual operation of the electronic device and the test circuit operates during a test of the electronic device. The device identifying method includes measuring electrical characteristics of a plurality of test elements, storing identification information of an electronic device by storing the measured electrical characteristics of the respective test elements, obtaining identification information of a certain electronic device by measuring electrical characteristics of a plurality of test elements provided in the certain electronic device in order to identify the certain electronic device, comparing the identification information obtained in the identification information obtaining with the identification information stored in the identification information storing, and, when the obtained identification information matches the stored identification information, judging that the certain electronic device is the same as the electronic device associated with the stored identification information.
摘要翻译：提供一种用于识别其中包括实际操作电路的电子设备的装置识别方法和其中设置有多个测试元件的测试电路，其中实际操作电路在电子设备的实际操作期间操作并且测试电路操作在电子设备的测试期间。设备识别方法包括测量多个测试元件的电特性，通过存储所测量的各个测试元件的电特性来存储电子设备的识别信息，通过测量多个测试元件的电特性来获得某个电子设备的识别信息在特定电子设备中提供的测试元件，以识别某个电子设备，将获得的识别信息与存储在识别信息中的识别信息进行比较，并且当获得的识别信息与存储的识别信息相匹配时判断该电子装置与存储的识别信息相关联的电子装置相同。

58. 发明授权

US07795106B2 Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof 有权
标题翻译：在Si晶体的（111）表面上形成的半导体器件及其制造方法
公开(公告)号：US07795106B2
公开(公告)日：2010-09-14
申请号：US11907348
申请日：2007-10-11
申请人： Tadahiro Ohmi , Shigetoshi Sugawa , Katsuyuki Sekine , Yuji Saito
发明人： Tadahiro Ohmi , Shigetoshi Sugawa , Katsuyuki Sekine , Yuji Saito
IPC分类号： H01L21/76
CPC分类号： H01L21/28185 , G11C11/16 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28238 , H01L21/28291 , H01L27/11521 , H01L27/11585 , H01L27/1159 , H01L27/1203 , H01L29/045 , H01L29/4908 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/7833 , H01L29/78603 , H01L29/78612 , H01L29/7883
摘要： A semiconductor device includes a Si crystal having a crystal surface in the vicinity of a (111) surface, and an insulation film formed on said crystal surface, at least a part of said insulation film comprising a Si oxide film containing Kr or a Si nitride film containing Ar or Kr.
摘要翻译：半导体器件包括在（111）表面附近具有晶体表面的Si晶体和形成在所述晶体表面上的绝缘膜，所述绝缘膜的至少一部分包括含有Kr或Si氮化物的Si氧化物膜含Ar或Kr的薄膜。

59. 发明授权

US07774081B2 Manufacturing system, manufacturing method, managing apparatus, managing method and computer readable medium 失效
标题翻译：制造系统，制造方法，管理装置，管理方法和计算机可读介质
公开(公告)号：US07774081B2
公开(公告)日：2010-08-10
申请号：US12046457
申请日：2008-03-12
申请人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
发明人： Toshiyuki Okayasu , Shigetoshi Sugawa , Akinobu Teramoto
IPC分类号： G06F19/00 , G01N37/00 , G11C16/04 , H01R31/26 , H01L21/66
CPC分类号： G05B19/41875 , G05B2219/32221 , G05B2219/45031 , H01L22/20 , H01L22/34 , H01L2924/0002 , Y02P90/22 , H01L2924/00
摘要： There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing apparatuses performing processes corresponding to the plurality of manufacturing stages. The manufacturing system includes a manufacturing line that manufactures the electronic device, a manufacturing control section that causes the manufacturing line to manufacture a wafer having therein a test circuit including a plurality of transistors under measurement, a measuring section that measures an electrical characteristic of each of the plurality of transistors under measurement in the test circuit, an identifying section that identifies, among the plurality of manufacturing stages, a manufacturing stage in which a defect is generated, with reference to a distribution, on the wafer, of one or more transistors under measurement whose electrical characteristics do not meet a predetermined standard, and a setting changing section that changes a setting for a manufacturing apparatus that performs a process corresponding to the manufacturing stage in which the defect is generated.
摘要翻译：提供了一种用于通过多个制造阶段制造电子装置的制造系统。制造系统包括执行与多个制造阶段相对应的处理的多个制造装置。制造系统包括制造电子装置的制造线，使制造线制造其中具有测量电路的测试电路的晶片的制造控制部，测量各测量电路的电特性的测量部在测试电路中测量的多个晶体管，识别部分，其在多个制造阶段中，根据晶片上的一个或多个晶体管的分布，识别其中产生缺陷的制造阶段电气特性不符合预定标准的测量值，以及改变执行与生成缺陷的制造阶段相对应的处理的制造装置的设定的设定变更部。

60. 发明申请

US20090073291A1 SOLID-STATE IMAGING DEVICE 有权
标题翻译：固态成像装置
公开(公告)号：US20090073291A1
公开(公告)日：2009-03-19
申请号：US12264972
申请日：2008-11-05
申请人： Tomoya Yoneda , Shigetoshi Sugawa , Toru Koizumi , Tetsunobu Kochi
发明人： Tomoya Yoneda , Shigetoshi Sugawa , Toru Koizumi , Tetsunobu Kochi
IPC分类号： H04N5/335
CPC分类号： H04N1/195 , H01L27/14603 , H01L27/14609 , H01L27/14623 , H01L27/14643
摘要： To control the potential distribution generated in a well at the time of amplification and reduce a shading in a solid-state imaging device of amplification type, the amplification type solid-state imaging device of the present invention comprises a plurality of picture elements each including photoelectric conversion elements formed in a second conductivity type common well inside a first conductivity type substrate, wherein a plurality of well contacts are disposed inside a picture element array area.
摘要翻译：为了控制放大时在阱中产生的电位分布并减小放大型固态成像装置中的阴影，本发明的放大型固态成像装置包括多个图像元素，每个图像元素包括光电形成在第一导电型衬底内的第二导电类型共同阱中的转换元件，其中多个阱触点设置在像素阵列区域内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式