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    • 53. 发明申请
    • PROPORTIONAL MEMORY OPERATION THROTTLING
    • 比例存储器操作曲线
    • US20130054901A1
    • 2013-02-28
    • US13217513
    • 2011-08-25
    • Sukalpa BiswasHao Chen
    • Sukalpa BiswasHao Chen
    • G06F12/00
    • G06F13/1642
    • A memory controller receives memory operations via an interface which may include multiple ports. Each port is coupled to real-time or non-real-time requestors, and the received memory operations are classified as real-time or non-real-time and stored in queues prior to accessing memory. Within the memory controller, pending memory operations from the queues are scheduled for servicing. Logic throttles the scheduling of non-real-time memory operations in response to detecting a number of outstanding memory operations has exceeded a threshold. The throttling is proportional to the number of outstanding memory operations.
    • 存储器控制器经由可以包括多个端口的接口来接收存储器操作。 每个端口耦合到实时或非实时请求者,并且所接收的存储器操作被分类为实时或非实时的,并且在访问存储器之前存储在队列中。 在内存控制器中,排队等待的内存操作计划进行维修。 响应于检测到未完成的存储器操作的数量已经超过阈值,逻辑控制非实时存储器操作的调度。 节流与未完成记忆操作的数量成比例。
    • 54. 发明授权
    • Hybrid element enabling solid/SPH coupling effect
    • 混合元件可实现固体/ SPH耦合效应
    • US08374833B2
    • 2013-02-12
    • US12815112
    • 2010-06-14
    • Hao ChenJingxiao XuChi-Hsien Wang
    • Hao ChenJingxiao XuChi-Hsien Wang
    • G06G7/48
    • G06F17/5095G06F17/5018G06F2217/16Y02T10/82
    • Hybrid elements that enable coupling effects between SPH particles and FEM solid are disclosed. According to one aspect of the present invention, hybrid elements are configured to facilitate coupling effect of solid element based on finite element method (FEM) and one or more corresponding particles based on smoothed particle hydrodynamics (SPH). Hybrid elements are defined in a computer aided engineering (CAE) grid model as a buffer or interface between the SPH particles and FEM solids. For example, a portion of the grid model comprises SPH particles because the likelihood of enduring large deformation, while the rest of the model comprises FEM solid elements. Hybrid elements are placed between the solids and the particles. Each hybrid element comprises two layers: solid layer and particle layer.
    • 公开了能够实现SPH颗粒和FEM固体之间耦合效应的混合元件。 根据本发明的一个方面,混合元件构造成有助于基于有限元法(FEM)和基于平滑颗粒流体动力学(SPH)的一个或多个相应颗粒的固体元素的耦合效应。 混合元素在计算机辅助工程(CAE)网格模型中定义为SPH粒子和FEM固体之间的缓冲区或界面。 例如,网格模型的一部分包含SPH粒子,因为持续大变形的可能性,而模型的其余部分包括有限元实​​体元素。 将混合元件放置在固体和颗粒之间。 每个混合元件包括两层:固体层和颗粒层。
    • 57. 发明授权
    • Memory controller with loopback test interface
    • 带环回测试接口的内存控制器
    • US08301941B2
    • 2012-10-30
    • US13305202
    • 2011-11-28
    • Luka BodrozicSukalpa BiswasHao ChenSridhar P. SubramanianJames B. Keller
    • Luka BodrozicSukalpa BiswasHao ChenSridhar P. SubramanianJames B. Keller
    • G01R31/28G11C29/00G06F11/00
    • G01R31/31716
    • An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    • 设备可以包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可以由处理器编程成环回测试操作模式,并且在回送测试模式中,存储器控制器可以被配置为通过互连从处理器接收第一写入操作。 存储器控制器可以被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 存储器控制器还可以被配置为在互连上将读数据作为读数据返回,用于从互连上的处理器接收到的第一读操作。
    • 59. 发明申请
    • System for Automatically Adjusting Sound Effects and Method Thereof
    • 自动调节声音效果及方法的系统
    • US20120186418A1
    • 2012-07-26
    • US13359161
    • 2012-01-26
    • Hao ChenYun-Fei Wei
    • Hao ChenYun-Fei Wei
    • G10H1/02
    • G10H1/0091G10H1/46G10H2240/145
    • A system for automatically adjusting sound effects and a method thereof. The system includes a communication module, a playing module, an input module for receiving a choice among a plurality of songs made by a user, and a processing module configured to search a storage module for one of sets of sound effects parameters corresponding to the choice made by the user. If the set of sound effects parameters corresponding to the choice made by the user is not found, the processing module is then configured to obtain the set of sound effects parameters from a plurality of servers through a communication module. The playing module is configured to adjust a playing mode according to the set of sound effects parameters found or obtained by the processing module, and to play the song of choice in the playing mode.
    • 一种用于自动调节声音效果的系统及其方法。 该系统包括通信模块,播放模块,用于接收由用户制作的多首歌曲中的选择的输入模块以及配置成搜索存储模块中与选择对应的一组声音效果参数之一的处理模块 由用户制作 如果没有找到与用户做出的选择相对应的一组声音效果参数,则处理模块然后被配置为通过通信模块从多个服务器获得一组声音效果参数。 播放模块被配置为根据由处理模块找到或获得的声音效果参数的集合来调整播放模式,并且在播放模式下播放所选择的歌曲。
    • 60. 发明申请
    • Mechanism for an Efficient DLL Training Protocol During a Frequency Change
    • 频率变化期间高效率的DLL训练协议的机制
    • US20120126868A1
    • 2012-05-24
    • US12951788
    • 2010-11-22
    • Erik P. MachnickiHao ChenSanjay Mansingh
    • Erik P. MachnickiHao ChenSanjay Mansingh
    • H03L7/06
    • H03L7/07H03L7/0814
    • An efficient delay locked loop (DLL) training protocol during a frequency change includes an integrated circuit with a memory physical layer (PHY) unit that includes a master DLL and a slave DLL. The master DLL may delay a first reference clock by an amount, and provide a reference delay value corresponding to the delay amount. The slave DLL may delay a second reference clock by a second amount based upon a received configuration delay value. An interface unit may generate the configuration delay value based upon the reference delay value. A power management unit may provide an indication that the frequency of the second reference clock is changing. In response to receiving the indication, the interface unit may generate a new configuration delay value that corresponds to the new frequency using a predetermined scaling value and provide the new configuration delay value to the memory PHY unit.
    • 在频率变化期间,有效的延迟锁定环(DLL)训练协议包括具有包含主DLL和从属DLL的存储器物理层(PHY)单元的集成电路。 主DLL可以将第一参考时钟延迟一定量,并提供对应于延迟量的参考延迟值。 从属DLL可以基于接收的配置延迟值将第二参考时钟延迟第二量。 接口单元可以基于参考延迟值生成配置延迟值。 功率管理单元可以提供第二参考时钟的频率正在改变的指示。 响应于接收到指示,接口单元可以使用预定的缩放值来生成对应于新频率的新的配置延迟值,并向存储器PHY单元提供新的配置延迟值。