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51. 发明授权

US08035198B2 Through wafer via and method of making same 有权
标题翻译：通过晶片通孔及其制作方法
公开(公告)号：US08035198B2
公开(公告)日：2011-10-11
申请号：US12188229
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L21/768 , H01L23/538
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/0401 , H01L2224/04026 , H01L2224/0405 , H01L2224/0557 , H01L2224/06181 , H01L2224/11002 , H01L2224/11003 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/81191 , H01L2224/81192 , H01L2225/06513 , H01L2225/06541 , H01L2924/01068 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/00
摘要： A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.
摘要翻译：通过晶片通孔结构。该结构包括：具有顶表面和相对底表面的半导体衬底; 以及贯穿晶片通孔的阵列，其包括至少一个导电的通过晶片通孔和至少一个非导电的通过晶片通孔，每个通过晶片通孔的通过晶片通孔的阵列从基板的顶表面延伸到更大的比一半到一路到底层的底面。也是用于制造晶片通孔结构的方法。

52. 发明授权

US08028406B2 Methods of fabricating coplanar waveguide structures 有权
标题翻译：制造共面波导结构的方法
公开(公告)号：US08028406B2
公开(公告)日：2011-10-04
申请号：US12061861
申请日：2008-04-03
申请人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
发明人： Hanyi Ding , Essam F. Mina , Guoan Wang , Wayne H. Woods
IPC分类号： H05K3/10 , H01P11/00 , H01P3/00
CPC分类号： H01P11/003 , H01P3/003 , Y10T29/49016 , Y10T29/49155 , Y10T29/49162
摘要： Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array. Each of the second plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.
摘要翻译：制造共面波导结构的方法。该方法可以包括在第一和第二接地导体之间的共面布置中形成第一和第二接地导体和信号导体，在信号导体和第一和第二接地导体之上形成基本上平行的屏蔽导体的第一共面阵列，并形成在信号导体和第一和第二接地导体下面的基本上平行的屏蔽导体的第二共面阵列。该方法还包括形成位于信号导体和第一接地导体之间横向定位的第一多个导电桥，以及形成位于信号导体和第二接地导体之间横向定位的第二多个导电桥。第一多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。第二多个导电桥中的每一个将第一阵列中的一个屏蔽导体与第二阵列中的屏蔽导体中的一个连接。

53. 发明授权

US08012814B2 Method of forming a high performance fet and a high voltage fet on a SOI substrate 有权
标题翻译：在SOI衬底上形成高性能fet和高电压fet的方法
公开(公告)号：US08012814B2
公开(公告)日：2011-09-06
申请号：US12188366
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823462 , H01L21/823481 , H01L27/1203 , H01L27/1207
摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.
摘要翻译：保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

54. 发明申请

US20100035370A1 INTEGRATED MILLIMETER WAVE ANTENNA AND TRANSCEIVER ON A SUBSTRATE 有权
标题翻译：集成的毫米波天线和基座上的收发器
公开(公告)号：US20100035370A1
公开(公告)日：2010-02-11
申请号：US12187436
申请日：2008-08-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01L21/00
CPC分类号： H01Q1/40 , H01Q9/28
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器形成在半导体衬底的前侧。至少一个通过衬底通孔提供收发器和半导体衬底的背面之间的电连接。连接到收发器的天线形成在前侧的电介质层中。反射板与穿通基板连接，并形成在背面。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。通过衬底沟槽的阵列可以形成并填充介电材料，以减小天线和反射板之间的材料的有效介电常数，从而减小毫米波的波长并提高辐射效率。

55. 发明申请

US20100032810A1 THROUGH WAFER VIAS AND METHOD OF MAKING SAME 有权
标题翻译：通过WAVER VIAS及其制作方法
公开(公告)号：US20100032810A1
公开(公告)日：2010-02-11
申请号：US12188236
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L23/66 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2223/6616 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。通过晶片通孔形成的方法包括通过半导体衬底形成贯穿晶片通孔的阵列，其包括至少一个导电晶片通孔和至少一个不导电的晶片通孔，该半导体衬底具有顶表面和相对的底表面通过晶片通孔从衬底的顶表面延伸到衬底的底表面的通过晶片通孔的阵列。

56. 发明申请

US20100032761A1 SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US20100032761A1
公开(公告)日：2010-02-11
申请号：US12188381
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

57. 发明申请

US20060186983A1 On-chip inductor with magnetic core 有权
标题翻译：带磁芯的片上电感
公开(公告)号：US20060186983A1
公开(公告)日：2006-08-24
申请号：US11400669
申请日：2006-04-07
申请人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01F27/28
CPC分类号： H01F41/046 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An inductor formed on an integrated circuit chip including one or more inner layers between two or more outer layers, inductor metal winding turns included in one or more inner layers, and a magnetic material forming the two or more outer layers and the one or more inner layers. In one embodiment, the magnetic material is a photoresist paste having magnetic particles. In another embodiment, the magnetic material is a series of magnetic metallic strips disposed on each of first and second portions of the two or more outer layers and on each of the one or more inner layers. The series of magnetic metallic strips on the first and second portions form a grid pattern. Other embodiments include an adjustable controlled compound deposit and control windings with adjustable electrical currents.
摘要翻译：形成在集成电路芯片上的电感器，其包括在两个或多个外层之间的一个或多个内层，包括在一个或多个内层中的电感器金属绕组匝以及形成两个或更多个外层的磁性材料和一个或多个内层层。在一个实施例中，磁性材料是具有磁性颗粒的光致抗蚀剂浆料。在另一个实施例中，磁性材料是设置在两个或多个外层的第一和第二部分中的每一个上以及一个或多个内层中的每一个上的一系列磁性金属条。第一和第二部分上的一系列磁性金属条形成网格图案。其他实施例包括具有可调电流的可调控制的化合物沉积和控制绕组。

58. 发明授权

US08589832B2 On chip shielding structure for integrated circuits or devices on a substrate and method of shielding 有权
标题翻译：用于集成电路或基板上的器件的片上屏蔽结构和屏蔽方法
公开(公告)号：US08589832B2
公开(公告)日：2013-11-19
申请号：US11844397
申请日：2007-08-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： H05K9/0022
摘要： An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.
摘要翻译：一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。

59. 发明授权

US08519892B2 Integrated millimeter wave antenna and transceiver on a substrate 有权
标题翻译：集成毫米波天线和收发器在基板上
公开(公告)号：US08519892B2
公开(公告)日：2013-08-27
申请号：US13534350
申请日：2012-06-27
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01Q1/38 , H01Q19/10
CPC分类号： H01Q1/2283 , H01Q1/40 , H01Q9/26 , H01Q9/285 , H01Q19/108 , H01Q19/30
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器位于半导体衬底的前侧。通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。连接到收发器的天线位于位于基板正面的电介质层中。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

60. 发明授权

US08384224B2 Through wafer vias and method of making same 有权
标题翻译：通过晶圆通孔及其制作方法
公开(公告)号：US08384224B2
公开(公告)日：2013-02-26
申请号：US12188241
申请日：2008-08-08
申请人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
发明人： Hanyi Ding , Alvin Jose Joseph , Anthony Kendall Stamper
IPC分类号： H01L29/40
CPC分类号： H01L21/76802 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L24/05 , H01L24/10 , H01L24/12 , H01L24/13 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/2518 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1305 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/00 , H01L2224/05552
摘要： A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.
摘要翻译：用于通过晶片通孔形成和结构的方法，所述晶片通孔和通过晶片通孔形成的信号传输线。该结构包括：具有顶表面和相对底表面的半导体衬底; 以及贯穿晶片通孔的阵列，其包括至少一个导电的通过晶片通孔和至少一个非导电的通过晶片通孔，每个通过晶片通孔的通过晶片通孔的阵列从顶表面延伸到底表面所述衬底，所述至少一个导电通孔与所述衬底电隔离。

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