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1. 发明申请

US20120132992A1 SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US20120132992A1
公开(公告)日：2012-05-31
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

2. 发明申请

US20100035390A1 METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成高性能FET和高电压FET的方法
公开(公告)号：US20100035390A1
公开(公告)日：2010-02-11
申请号：US12188366
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823462 , H01L21/823481 , H01L27/1203 , H01L27/1207
摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.
摘要翻译：保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

3. 发明申请

US20090317975A1 METHOD FOR FORMING AN 0N-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
标题翻译：用于形成0N芯片高频电静电放电装置的方法
公开(公告)号：US20090317975A1
公开(公告)日：2009-12-24
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/311
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属水平布线的晶片，并且在其中形成气密密封的间隙以为集成电路提供静电放电保护。

4. 发明申请

US20090317970A1 METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：用于形成片上高频电静电放电装置的方法
公开(公告)号：US20090317970A1
公开(公告)日：2009-12-24
申请号：US12144089
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.
摘要翻译：描述了在集成电路上形成片上高频静电放电装置的方法。在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。在封盖的第一介电层上沉积第二介电层。第一硬掩模介电层沉积在第二介电层上。通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。至少一个通孔围绕腔沟槽形成穿过第二电介质层。在所述至少一个通孔中的每一个周围形成金属沟槽。在空腔沟槽上形成释放开口。在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

5. 发明申请

US20090316314A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316314A1
公开(公告)日：2009-12-24
申请号：US12144095
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。其中形成有多于一个电极的第二电介质层位于第一介电层的上方。至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

6. 发明授权

US07564319B2 Vertical LC tank device 失效
标题翻译：垂直液相色谱槽装置
公开(公告)号：US07564319B2
公开(公告)日：2009-07-21
申请号：US11859850
申请日：2007-09-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H03B5/08 , H01F5/00 , H01L29/00
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译：一种LC粘结结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

7. 发明授权

US08589832B2 On chip shielding structure for integrated circuits or devices on a substrate and method of shielding 有权
标题翻译：用于集成电路或基板上的器件的片上屏蔽结构和屏蔽方法
公开(公告)号：US08589832B2
公开(公告)日：2013-11-19
申请号：US11844397
申请日：2007-08-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： H05K9/0022
摘要： An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.
摘要翻译：一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。

8. 发明授权

US08519892B2 Integrated millimeter wave antenna and transceiver on a substrate 有权
标题翻译：集成毫米波天线和收发器在基板上
公开(公告)号：US08519892B2
公开(公告)日：2013-08-27
申请号：US13534350
申请日：2012-06-27
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01Q1/38 , H01Q19/10
CPC分类号： H01Q1/2283 , H01Q1/40 , H01Q9/26 , H01Q9/285 , H01Q19/108 , H01Q19/30
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器位于半导体衬底的前侧。通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。连接到收发器的天线位于位于基板正面的电介质层中。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

9. 发明申请

US20110132652A1 STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING 有权
标题翻译：基底噪声非常高的插入损耗的结构
公开(公告)号：US20110132652A1
公开(公告)日：2011-06-09
申请号：US13016126
申请日：2011-01-28
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H05K1/11 , H05K1/02
CPC分类号： H01L23/552 , H01L21/76 , H01L21/76264 , H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.
摘要翻译：一种结构包括具有对电噪声敏感的电路或器件的区域的衬底。此外，该结构包括延伸穿过衬底的整个厚度并围绕该区域的第一隔离结构，以及延伸穿过衬底的整个厚度并围绕该区域的第二隔离结构。

10. 发明授权

US07943404B2 Integrated millimeter wave antenna and transceiver on a substrate 有权
标题翻译：集成毫米波天线和收发器在基板上
公开(公告)号：US07943404B2
公开(公告)日：2011-05-17
申请号：US12187436
申请日：2008-08-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
IPC分类号： H01L21/00
CPC分类号： H01Q1/40 , H01Q9/28
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is formed on a front side of a semiconductor substrate. At least one through substrate via provides electrical connection between the transceiver and the backside of the semiconductor substrate. The antenna, which is connected to the transceiver, is formed in a dielectric layer on the front side. The reflector plate is connected to the through substrate via, and is formed on the backside. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate trenches may be formed and filled with a dielectric material to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency.
摘要翻译：提供集成收发器，天线和接收器的半导体芯片。收发器形成在半导体衬底的前侧。至少一个通过衬底通孔提供收发器和半导体衬底的背面之间的电连接。连接到收发器的天线形成在前侧的电介质层中。反射板与穿通基板连接，并形成在背面。反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。通过衬底沟槽的阵列可以形成并填充介电材料，以减小天线和反射板之间的材料的有效介电常数，从而减小毫米波的波长并提高辐射效率。

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