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51. 发明授权

US06916380B2 System for depositing a layered film 失效
标题翻译：用于沉积层状膜的系统
公开(公告)号：US06916380B2
公开(公告)日：2005-07-12
申请号：US10871965
申请日：2004-06-18
申请人： Haining Yang , Gurtej S. Sandhu
发明人： Haining Yang , Gurtej S. Sandhu
IPC分类号： C23C16/18 , H01L21/02 , H01L21/285 , H01L21/8242 , C23C16/00 , C23C16/52
CPC分类号： H01L28/75 , C23C16/18 , H01L21/28556 , H01L21/28568 , H01L27/1085 , H01L28/55 , H01L28/65 , H01L28/84 , H01L28/90
摘要： The present invention relates to an electrically conductive film stack for semiconductors and methods and apparatus for providing same. A film stack comprising a first layer of a platinum-rhodium alloy deposited by metal organic chemical vapor deposition (MOCVD) in the presence of a reducer, such as hydrogen (H2) gas, and a second layer of the platinum-rhodium alloy deposited in the presence of an oxidizing gas, such as ozone (O3), provides an electrical conductor that is also a relatively good barrier to oxygen. The platinum-rhodium film stack can be used as an electrode or capacitor plate for a capacitor with a high-k dielectric material. The electrode formed with alternating reducing and oxidizing agents produces a rough surface texture, which enhances the memory cell capacitance.
摘要翻译：本发明涉及一种用于半导体的导电膜叠层及其提供方法和装置。一种薄膜叠层，包括在还原剂例如氢（H 2/2））气体存在下通过金属有机化学气相沉积（MOCVD）沉积的铂 - 铑合金的第一层和第二层在氧化气体如臭氧（O 3 3 N）的存在下沉积的铂 - 铑合金提供了也是相对较好的氧阻挡层的电导体。铂 - 铑膜叠层可用作具有高k电介质材料的电容器的电极或电容器板。用交替的还原和氧化剂形成的电极产生粗糙的表面纹理，这增强了存储单元电容。

52. 发明申请

US20050093030A1 Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers 有权
标题翻译：使用不同种类的应力层来增强nFET和pFET性能的结构和方法
公开(公告)号：US20050093030A1
公开(公告)日：2005-05-05
申请号：US10695748
申请日：2003-10-30
申请人： Bruce Doris , Haining Yang , Huilong Zhu
发明人： Bruce Doris , Haining Yang , Huilong Zhu
IPC分类号： H01L21/8238 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
摘要翻译：在制造互补的金属氧化物半导体（CMOS）场效应晶体管（包括nMOS和pMOS晶体管）的情况下，通过使用在nMOS或pMOS晶体管（或两者）上分层各种应力薄膜来增强或调节载流子迁移率，取决于层的性质并且将应力层彼此隔离并且在所选位置具有附加层的其它结构。因此，单个芯片或衬底上的两种类型的晶体管可以实现增强的载流子迁移率，从而提高CMOS器件和集成电路的性能。

53. 发明申请

US20050051851A1 STRUCTURE AND METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS 有权
标题翻译：具有狭缝分离的外延延伸和源和漏区的应变通道CMOS晶体管的结构和方法
公开(公告)号：US20050051851A1
公开(公告)日：2005-03-10
申请号：US10605134
申请日：2003-09-10
申请人： Huajie Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
发明人： Huajie Chen , Dureseti Chidambarrao , Omer Dokumaci , Haining Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8238 , H01L29/78 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7848
摘要： A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.
摘要翻译：提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。应力由第一半导体晶格失配的第二半导体层施加。第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

54. 发明授权

US06740554B2 Methods to form rhodium-rich oxygen barriers 失效
标题翻译：形成富铑氧气屏障的方法
公开(公告)号：US06740554B2
公开(公告)日：2004-05-25
申请号：US10209386
申请日：2002-07-30
申请人： Haining Yang , Dan Gealy , Gurtej S. Sandhu , Howard Rhodes , Mark Visokay
发明人： Haining Yang , Dan Gealy , Gurtej S. Sandhu , Howard Rhodes , Mark Visokay
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： A structure and method are disclosed for forming a capacitor for an integrated circuit. The capacitor includes a rhodium-rich structure, a rhodium oxide layer in direct contact with the rhodium-rich structure, a capacitor dielectric in direct contact with the rhodium oxide layer and a top electrode over the capacitor. The rhodium-rich structure can include rhodium alloys and the capacitor dielectric preferably has a high dielectric constant.
摘要翻译：公开了一种用于形成用于集成电路的电容器的结构和方法。电容器包括富铑结构，与富铑结构直接接触的铑氧化物层，与氧化铑层直接接触的电容器电介质和电容器上的顶电极。富铑结构可以包括铑合金，并且电容器电介质优选具有高的介电常数。

55. 发明授权

US06693017B1 MIMcap top plate pull-back 有权
标题翻译： MIMcap顶板拉回
公开(公告)号：US06693017B1
公开(公告)日：2004-02-17
申请号：US10407587
申请日：2003-04-04
申请人： Mohammed Fazil Fayaz , Haining Yang , Uwe Kerst , Joseph J. Mezzapelle
发明人： Mohammed Fazil Fayaz , Haining Yang , Uwe Kerst , Joseph J. Mezzapelle
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L27/0805
摘要： A MIM capacitor includes a bottom plate, a capacitor dielectric disposed over the bottom plate, and a top plate disposed over the capacitor dielectric. An etch stop material is disposed over the top plate, and the top plate has a width that is less than the width of the etch stop material width. The top plate edges may be pulled back during the removal of the resist used to pattern the top plate, by the addition of chemistries in the resist etch that are adapted to pull-back or undercut the top plate edges beneath the etch stop material.
摘要翻译： MIM电容器包括底板，设置在底板上的电容器电介质和设置在电容器电介质上的顶板。蚀刻停止材料设置在顶板上方，并且顶板的宽度小于蚀刻停止材料宽度的宽度。在去除用于图案化顶板的抗蚀剂时，顶板边缘可以被拉回，通过在抗蚀剂蚀刻中添加适于在蚀刻停止材料下面的顶板边缘进行拉回或削切的化学物质。

56. 发明授权

US06642566B1 Asymmetric inside spacer for vertical transistor 失效
标题翻译：垂直晶体管的不对称内隔板
公开(公告)号：US06642566B1
公开(公告)日：2003-11-04
申请号：US10195601
申请日：2002-06-28
申请人： Jack A. Mandelman , Ramachandra Divakaruni , Haining Yang
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Haining Yang
IPC分类号： H01L2708
CPC分类号： H01L27/10876 , H01L27/10864 , H01L27/10888 , H01L27/10891
摘要： A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.
摘要翻译：具有使用垂直晶体管的DRAM单元的DRAM阵列通过在字线和晶体管之间的连接中使用不对称结构来增加电可靠性并降低位线电容，从而允许在字线和晶体管电极之间使用更宽的连接并且使用该字线作为蚀刻停止以在图形化字线期间保护晶体管栅极。

57. 发明授权

US06391801B1 Method of forming a layer comprising tungsten oxide 有权
标题翻译：形成包含氧化钨的层的方法
公开(公告)号：US06391801B1
公开(公告)日：2002-05-21
申请号：US09388731
申请日：1999-09-01
申请人： Haining Yang
发明人： Haining Yang
IPC分类号： H01L2131
CPC分类号： H01L21/02183 , H01L21/02326 , H01L21/28123 , H01L21/28202 , H01L21/28229 , H01L21/28568 , H01L21/3143 , H01L21/31683 , H01L28/40 , H01L28/56 , H01L29/4966 , H01L29/513 , H01L29/518 , H01L29/66568
摘要： The invention includes capacitors, capacitor forming methods, field effect transistors, and field effect transistor forming methods. In one aspect, a method of forming a layer including tungsten oxide includes forming a first layer including tungsten nitride over a substrate. In one implementation, the tungsten nitride is oxidized under conditions effective to form a second layer at least a majority of which is tungsten trioxide. In one aspect, a capacitor forming method includes forming a first capacitor electrode layer over a substrate. A second layer including tungsten nitride is formed over the first capacitor electrode layer. A third capacitor electrode layer is formed over the second layer. The second layer is oxidized under conditions effective to transform at least some of the tungsten nitride into a tungsten trioxide comprising capacitor dielectric layer. Other capacitor forming methods are contemplated. The invention also includes capacitors formed by these and other methods. In one aspect, a method of forming a field effect transistor includes forming a tungsten nitride comprising layer proximate at least one of a semiconductive channel region or a conductive gate layer. The tungsten nitride comprising layer is oxidized under conditions effective to transform at least some of the tungsten nitride to a tungsten oxide comprising gate dielectric layer. A transistor gate is provided operably proximate the gate dielectric layer, and source/drain regions are provided operably proximate the transistor gate.
摘要翻译：本发明包括电容器，电容器形成方法，场效应晶体管和场效应晶体管形成方法。一方面，形成包括氧化钨的层的方法包括在衬底上形成包括氮化钨的第一层。在一个实施方案中，氮化钨在有效形成第二层的条件下被氧化，其中至少大部分是三氧化钨。一方面，电容器形成方法包括在衬底上形成第一电容器电极层。在第一电容器电极层上形成包括氮化钨的第二层。在第二层上形成第三电容器电极层。在有效地将至少一些氮化钨转化成包含电容器介电层的三氧化钨的条件下，第二层被氧化。考虑其他电容器形成方法。本发明还包括由这些和其他方法形成的电容器。一方面，形成场效应晶体管的方法包括在半导体沟道区或导电栅层中的至少一个附近形成包含氮化钨的层。包含氮化钨的层在有效地将至少一些氮化钨转化为包含栅极电介质层的氧化钨的条件下被氧化。晶体管栅极可操作地设置在栅极电介质层附近，并且源极/漏极区域可操作地设置在晶体管栅极附近。

58. 发明申请

US20110188328A1 Systems and Methods for Writing to Multiple Port Memory Circuits 有权
标题翻译：写入多端口存储器电路的系统和方法
公开(公告)号：US20110188328A1
公开(公告)日：2011-08-04
申请号：US12699933
申请日：2010-02-04
申请人： Haining Yang , Zhongze Wang , ChangHo Jung
发明人： Haining Yang , Zhongze Wang , ChangHo Jung
IPC分类号： G11C7/00 , G11C8/16
CPC分类号： G11C8/16 , G11C11/412
摘要： A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.
摘要翻译：多端口RAM电路具有耦合到多个位线和多个位线条的数据输入线。电路也有多条字线。存储单元耦合到位线，位线条和字线。电路还包括控制器，使得字线能够基本上同时从位线写入存储单元。

59. 发明申请

US20110003473A1 STRUCTURE FOR METAL CAP APPLICATIONS 有权
标题翻译：金属盖应用结构
公开(公告)号：US20110003473A1
公开(公告)日：2011-01-06
申请号：US12881806
申请日：2010-09-14
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76849
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

60. 发明授权

US07772119B2 Dual liner capping layer interconnect structure 失效
公开(公告)号：US07772119B2
公开(公告)日：2010-08-10
申请号：US12186923
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

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