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51. 发明申请

US20070035326A1 MEMORY CHIP AND METHOD FOR OPERATING A MEMORY CHIP 有权
标题翻译：记忆芯片和操作记忆芯片的方法
公开(公告)号：US20070035326A1
公开(公告)日：2007-02-15
申请号：US11461380
申请日：2006-07-31
申请人： Georg Braun , Christian Weis , Eckehard Plaettner
发明人： Georg Braun , Christian Weis , Eckehard Plaettner
IPC分类号： H03K19/003
CPC分类号： G11C7/1048 , G06F13/4086 , G11C5/04
摘要： Methods and apparatus for setting various terminations of a memory chip. In one embodiment, the memory chip includes a terminal, a termination circuit that can be connected to the terminal in order to terminate the terminal with a settable resistance value, a control command port for receiving a control command signal, and a control circuit that is connected to the termination circuit in order to set a resistance value as a function of a received control command signal.
摘要翻译：用于设置存储芯片的各种终端的方法和装置。在一个实施例中，存储器芯片包括终端，可以连接到终端以终止具有可设置电阻值的终端的终端电路，用于接收控制命令信号的控制命令端口，以及控制电路，连接到终端电路，以便根据接收到的控制命令信号设置电阻值。

52. 发明授权

US06833731B1 Electronic circuit for a method for storing information, said circuit comprising ferroelectric flip-flops 失效
标题翻译：用于存储信息的方法的电子电路，所述电路包括铁电触发器
公开(公告)号：US06833731B1
公开(公告)日：2004-12-21
申请号：US10070025
申请日：2002-05-14
申请人： Christl Lauterbach , Georg Braun , Udo Ollert , Werner Weber
发明人： Christl Lauterbach , Georg Braun , Udo Ollert , Werner Weber
IPC分类号： H03K1900
CPC分类号： G01F15/06 , H03K3/356086 , H03K3/45
摘要： A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure. The present invention relates to an electronic circuit which is provided with an input (5) for inputting at least one information signal, an energy means (2) for converting the energy that is present in the at least one information signal into a supply voltage, a control means (3) for generating at least one switch-on control signal when the information signal is input and a signal processing means (4) for storing information which is represented by the at least one information signal and/or for evaluating information which is represented by the at least one information signal and for storing the secondary information which is obtained by the evaluation. At least one ferroelectric flipflop (26) is used. The signal processing means (4) can be activated by the at least one switch-on control signal for evaluating and/or storing purposes. The at least one information signal can be or is the only energy source for the electronic circuit (1) during the evaluation and/or storing process.
摘要翻译：在用于处理信号的常规电子电路中需要电源电压，例如计数脉冲。电源电压供给逻辑电路元件。特别是必须在更长的时间段内或/和远程使用场所操作并且取决于电源电压的装置会受到依赖性相关缺点的损害，例如昂贵的EEPROM的必要性或显着增加的维护费用。本发明涉及一种电子电路，其具有用于输入至少一个信息信号的输入端（5），用于将存在于至少一个信息信号中的能量转换为电源电压的能量装置（2）用于当输入信息信号时产生至少一个接通控制信号的控制装置（3）和用于存储由至少一个信息信号表示的信息和/或用于评估信息的信息的信号处理装置（4）由所述至少一个信息信号表示，并且用于存储通过评估获得的次要信息。至少使用一个铁电触发器（26）。信号处理装置（4）可以被至少一个接通控制信号激活，用于评估和/或存储目的。在评估和/或存储过程期间，至少一个信息信号可以是或是电子电路（1）的唯一能量源。

53. 发明授权

US06560732B2 Operating method for an integrated memory having writeable memory cells and corresponding integrated memory 有权
公开(公告)号：US06560732B2
公开(公告)日：2003-05-06
申请号：US09963006
申请日：2001-09-25
申请人： Thomas Boehm , Georg Braun
发明人： Thomas Boehm , Georg Braun
IPC分类号： G11C2900
CPC分类号： G11C29/52
摘要： Before a write and/or read access to one of the memory cells is carried out, a security information stored in a security memory cell is read out. If the security information is characterized by a first logic state an error signal is generated. If the read-out security information is characterized by a second logic state the memory cell is accessed and a write access is carried out to the security memory cell during which a new security information to be he stored having the second logic state is written to the cell.

54. 发明授权

US06538950B2 Integrated memory and corresponding operating method 有权
公开(公告)号：US06538950B2
公开(公告)日：2003-03-25
申请号：US09917553
申请日：2001-07-27
申请人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
发明人： Thomas Böhm , Heinz Hönigschmid , Georg Braun , Zoltan Manyoki , Stefan Lammers , Thomas Rohr
IPC分类号： G11C800
CPC分类号： G11C7/06 , G11C7/065 , G11C7/1006
摘要： An integrated memory has a multiplexer and a differential sense amplifier with a differential input. The differential sense amplifier is connected to three bit lines by the multiplexer. The multiplexer electrically connects the differential input of the sense amplifier to any two of the three bit lines connected to it respectively, in accordance with its activation.

55. 发明授权

US06480055B2 Decoder element for generating an output signal having three different potentials and an operating method for the decoder element 有权
标题翻译：用于产生具有三个不同电位的输出信号的解码器元件和用于解码器元件的操作方法
公开(公告)号：US06480055B2
公开(公告)日：2002-11-12
申请号：US09822028
申请日：2001-03-29
申请人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
发明人： Thomas Böhm , Georg Braun , Heinz Hönigschmid , Zoltan Manyoki , Ernst Neuhold , Thomas Röhr
IPC分类号： H03K1776
CPC分类号： G11C5/143 , G11C8/08 , G11C16/12 , H03K19/09425 , H03M5/16
摘要： A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.
摘要翻译：解码器元件设置有输出，由此产生具有三种不同可能电位之一的输出信号。输出信号可以具有第一电位，第二电位和第三电位的值，其中第二电位位于第一电位和第三电位之间。输出信号根据解码器元件的端子连接处的输入信号的电压值而产生。

56. 发明授权

US06434039B1 Circuit configuration for reading a memory cell having a ferroelectric capacitor 有权
标题翻译：用于读取具有铁电电容器的存储单元的电路配置
公开(公告)号：US06434039B1
公开(公告)日：2002-08-13
申请号：US09838750
申请日：2001-04-19
申请人： Georg Braun , Heinz Hönigschmid
发明人： Georg Braun , Heinz Hönigschmid
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A circuit configuration for reading a ferroelectric memory cell which has a ferroelectric capacitor is described. The memory cell is connected to a bit line. The circuit configuration provides a differential amplifier having a first differential amplifier input, a second differential amplifier input and a differential amplifier output. The first differential amplifier input is connected to the bit line, and the second differential amplifier input is connected to a reference signal. A first driver input of a first driver circuit is connected to the differential amplifier output, and a first driver output is connected to the bit line. The differential amplifier is fed back through the first driver circuit and regulates the bit line voltage to the voltage value of the reference signal.
摘要翻译：描述用于读取具有铁电电容器的铁电存储单元的电路结构。存储单元连接到位线。电路配置提供了具有第一差分放大器输入，第二差分放大器输入和差分放大器输出的差分放大器。第一差分放大器输入连接到位线，第二差分放大器输入连接到参考信号。第一驱动电路的第一驱动器输入端连接到差分放大器输出，第一驱动器输出端连接到位线。差分放大器通过第一驱动电路反馈，并将位线电压调节到参考信号的电压值。

57. 发明授权

US06396750B2 Integrated memory with redundancy and method for repairing an integrated memory 失效
公开(公告)号：US06396750B2
公开(公告)日：2002-05-28
申请号：US09888022
申请日：2001-06-22
申请人： Heinz Hönigschmid , Georg Braun , Andrej Majdic
发明人： Heinz Hönigschmid , Georg Braun , Andrej Majdic
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C29/702
摘要： An integrated memory has a normal bit line for transferring data from or to normal memory cells connected to it, and also a normal sense amplifier, which is connected via a line to the normal bit line and connected to a data line and amplifies data read from the normal memory cells. Furthermore, the memory has a redundant sense amplifier for replacing the normal sense amplifier in the redundancy situation. The redundant sense amplifier is likewise connected on the one hand to the line and on the other hand to the data line and, in the redundancy situation, serves for amplifying the data read from the normal memory cells. A method for repairing an integrated memory is also provided.

58. 发明授权

US07440349B2 Integrated semiconductor memory with determination of a chip temperature 失效
标题翻译：集成半导体存储器，具有芯片温度的测定
公开(公告)号：US07440349B2
公开(公告)日：2008-10-21
申请号：US11635088
申请日：2006-12-07
申请人： Georg Braun , Aaron Nygren
发明人： Georg Braun , Aaron Nygren
IPC分类号： G11C7/04 , G11C5/00 , G11C7/00 , G11C17/18
CPC分类号： G11C7/04 , G11C7/24 , G11C11/4063 , G11C11/4078
摘要： An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.
摘要翻译：能够确定芯片温度的集成半导体存储器包括用于驱动集成半导体存储器的第一控制端子，其具有用于执行写访问的第一控制信号和用于执行读访问的第二控制端。集成半导体还包括用于控制写入和读取访问的控制电路。用于记录集成半导体存储器的芯片温度的温度传感器连接到控制电路。控制电路被配置为以取决于温度传感器记录的温度的方式在第一或第一控制端子中的一个处产生第三控制信号的状态。

59. 发明申请

US20080143386A1 CONCEPT FOR INTERFACING A FIRST CIRCUIT REQUIRING A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY CIRCUIT REQUIRING A SECOND SUPPLY VOLTAGE 有权
标题翻译：用于接收需要第一电源电压的第一电路和需要第二电源电压的第二电源电路的概念
公开(公告)号：US20080143386A1
公开(公告)日：2008-06-19
申请号：US11641545
申请日：2006-12-19
申请人： Georg Braun , Dirk Scheideler , Steve Wood , Richard Johannes Luyken , Edoardo Prete , Hans-Peter Trost , Anthony Sanders
发明人： Georg Braun , Dirk Scheideler , Steve Wood , Richard Johannes Luyken , Edoardo Prete , Hans-Peter Trost , Anthony Sanders
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.
摘要翻译：使用第一电源电压的第一电路和使用不同于第一电源电压的第二电源电压的第二电路来连接设备。该装置包括具有驱动器网络的驱动器电路，驱动器网络包括连接到可控开关的驱动器电源电压可控开关包括电阻元件或与电阻元件分离。接收器电路具有包括电阻元件和接收器电源电压端子的接收网络以及连接驱动电路和接收电路的连接线。可控开关具有两个开关配置，第一开关配置导致连接线上的高电压，以及导致连接线上的低电压的第二开关配置。

60. 发明授权

US06911732B2 Integrated circuit 失效
标题翻译：集成电路
公开(公告)号：US06911732B2
公开(公告)日：2005-06-28
申请号：US10137511
申请日：2002-04-30
申请人： Simon Muff , Martin Gall , Andre Schaefer , Georg Braun
发明人： Simon Muff , Martin Gall , Andre Schaefer , Georg Braun
IPC分类号： H01L23/34 , H01L23/495 , H01L23/50 , H01L23/66
CPC分类号： H01L23/66 , H01L2224/49175 , H01L2924/15173 , H01L2924/30107 , H01L2924/00
摘要： An integrated circuit which is integrated in a housing having connecting pins fitted to the housing for connecting the housing to signal lines of an external circuit, each connecting pin connected by an associated wiring line to a contact pad of the circuit integrated in the housing, to exchange signals between the external circuit and the integrated circuit, where to minimize the line lengths of the associated wiring lines, the connecting pins to be connected to signal lines for high-frequency signals are fitted centrally to the housing.
摘要翻译：一种集成在壳体中的集成电路，其具有装配到壳体的连接销，用于将外壳连接到外部电路的信号线，每个连接引脚通过相关布线连接到集成在外壳中的电路的接触焊盘，在外部电路和集成电路之间交换信号，其中最小化相关布线的线路长度，要连接到用于高频信号的信号线的连接引脚被集中地安装到壳体。

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