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1. 发明授权

US07440349B2 Integrated semiconductor memory with determination of a chip temperature 失效
标题翻译：集成半导体存储器，具有芯片温度的测定
公开(公告)号：US07440349B2
公开(公告)日：2008-10-21
申请号：US11635088
申请日：2006-12-07
申请人： Georg Braun , Aaron Nygren
发明人： Georg Braun , Aaron Nygren
IPC分类号： G11C7/04 , G11C5/00 , G11C7/00 , G11C17/18
CPC分类号： G11C7/04 , G11C7/24 , G11C11/4063 , G11C11/4078
摘要： An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.
摘要翻译：能够确定芯片温度的集成半导体存储器包括用于驱动集成半导体存储器的第一控制端子，其具有用于执行写访问的第一控制信号和用于执行读访问的第二控制端。集成半导体还包括用于控制写入和读取访问的控制电路。用于记录集成半导体存储器的芯片温度的温度传感器连接到控制电路。控制电路被配置为以取决于温度传感器记录的温度的方式在第一或第一控制端子中的一个处产生第三控制信号的状态。

2. 发明申请

US20070133329A1 Integrated semiconductor memory with determination of a chip temperature 失效
标题翻译：集成半导体存储器，具有芯片温度的测定
公开(公告)号：US20070133329A1
公开(公告)日：2007-06-14
申请号：US11635088
申请日：2006-12-07
申请人： Georg Braun , Aaron Nygren
发明人： Georg Braun , Aaron Nygren
IPC分类号： G11C11/34
CPC分类号： G11C7/04 , G11C7/24 , G11C11/4063 , G11C11/4078
摘要： An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.
摘要翻译：能够确定芯片温度的集成半导体存储器包括用于驱动集成半导体存储器的第一控制端子，其具有用于执行写访问的第一控制信号和用于执行读访问的第二控制端。集成半导体还包括用于控制写入和读取访问的控制电路。用于记录集成半导体存储器的芯片温度的温度传感器连接到控制电路。控制电路被配置为以取决于温度传感器记录的温度的方式在第一或第一控制端子中的一个处产生第三控制信号的状态。

3. 发明申请

US20130159587A1 Interconnect Redundancy for Multi-Interconnect Device 审中-公开
标题翻译：多互连设备的互连冗余
公开(公告)号：US20130159587A1
公开(公告)日：2013-06-20
申请号：US13326663
申请日：2011-12-15
申请人： Aaron Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren F. Kruger
发明人： Aaron Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren F. Kruger
IPC分类号： G06F13/36
CPC分类号： G11C29/702 , G11C5/063
摘要： A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths.
摘要翻译：多互连集成电路装置包括用于通过配置I / O电路来输送多个交错数据信道组的输入/输出（I / O）电路，以在默认的固定互连信号路径上传送第一数据信道组，如果在默认固定互连信号路径中没有连接故障，并且如果在第一多个默认固定互连信号路径中存在至少一个连接故障，并且在第二多个默认固定互连信号路径上传送第一数据信道组，其中所述第二多个默认固定互连信号路径包括用于从所述第一多个默认固定互连信号路径替换故障互连信号路径的冗余固定互连信号路径。

4. 发明授权

US08161344B2 Circuits and methods for error coding data blocks 有权
标题翻译：用于错误编码数据块的电路和方法
公开(公告)号：US08161344B2
公开(公告)日：2012-04-17
申请号：US12046099
申请日：2008-03-11
申请人： Aaron Nygren
发明人： Aaron Nygren
IPC分类号： H03M13/00
CPC分类号： G11C7/1006 , G06F11/1004 , G11C7/24 , G11C2029/0411
摘要： A description is given of a circuit for creating an error coding data block for a first data block, including a first error coding path adapted to create the error coding data block in accordance with a first error coding; and a second error coding path adapted to create the error coding data block in accordance with a second error coding; the error coding data block for the first data block being created optionally by the first or second error coding paths, as a function of a control indicator, and at least the first error coding path comprising a data arrangement alteration device.
摘要翻译：给出了用于创建用于第一数据块的错误编码数据块的电路的描述，包括根据第一错误编码创建错误编码数据块的第一错误编码路径; 以及第二错误编码路径，其适于根据第二错误编码创建所述错误编码数据块; 由第一或第二错误编码路径可选地由第一或第二错误编码路径创建的第一数据块的错误编码数据块作为控制指示符的函数，并且至少包括数据排列改变装置的第一错误编码路径。

5. 发明授权

US07304495B2 Pseudodynamic off-chip driver calibration 有权
标题翻译：伪动态片外驱动器校准
公开(公告)号：US07304495B2
公开(公告)日：2007-12-04
申请号：US10975384
申请日：2004-10-29
申请人： Aaron Nygren
发明人： Aaron Nygren
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： A driver system, a driver calibration circuit arrangement for calibration of an impedance of a driver circuit arrangement, and a method for calibration of an impedance of a driver circuit arrangement can achieve improved driver behavior, with respect to undesirable distortions of the slew rate caused by off-chip drivers of DDR memory modules. A driver system has a first driver part with at least one variable impedance by which an operating point of the first driver part is determined with respect to a first potential and a second potential. The potentials supply the first driver part. A first monitoring device adjusts an impedance value of the variable impedance such that the operating point differs from a mid-point of the first and of the second potential.
摘要翻译：用于校准驱动器电路装置的阻抗的驱动器系统，驱动器校准电路装置以及用于校准驱动器电路装置的阻抗的方法可以相对于由不正确的由 DDR内存模块的片外驱动程序。驱动器系统具有至少一个可变阻抗的第一驱动器部分，通过该第一驱动器部分确定第一驱动器部分的工作点相对于第一电位和第二电位。潜力提供了第一个司机部分。第一监视装置调整可变阻抗的阻抗值，使得工作点与第一和第二电位的中点不同。

6. 发明申请

US20060197549A1 Chip to chip interface including assymetrical transmission impedances 审中-公开
标题翻译：芯片到芯片接口包括不对称传输阻抗
公开(公告)号：US20060197549A1
公开(公告)日：2006-09-07
申请号：US11072016
申请日：2005-03-04
申请人： Aaron Nygren
发明人： Aaron Nygren
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0175 , G11C7/1048 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C8/08 , G11C8/10 , G11C11/4093 , H04L25/0278
摘要： A chip to chip interface that includes a signal path and a first circuit. The first circuit includes asymmetrical transmission impedances to transmit high signals via the signal path using a first transmission impedance and low signals via the signal path using a second transmission impedance. The first transmission impedance and the second transmission impedance have different impedance values.
摘要翻译：包括信号路径和第一电路的芯片到芯片接口。第一电路包括通过使用第一传输阻抗的信号路径传输高信号的不对称传输阻抗和使用第二传输阻抗的信号路径的低信号。第一传输阻抗和第二传输阻抗具有不同的阻抗值。

7. 发明授权

US06946848B2 Calibration configuration 失效
标题翻译：校准配置
公开(公告)号：US06946848B2
公开(公告)日：2005-09-20
申请号：US10673965
申请日：2003-09-29
申请人： Andreas Täuber , Thomas Hein , Aaron Nygren
发明人： Andreas Täuber , Thomas Hein , Aaron Nygren
IPC分类号： G01R35/00 , G01R31/00 , G01R27/08 , G01R21/36
CPC分类号： G01R35/007
摘要： A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.
摘要翻译：用于设置可调阻抗的校准配置具有分压器，其具有可变电阻器和串联连接的电阻器，该电路被供给电源电压，并且在电阻器之间具有部分电压抽头端子。电路具有另一个电阻，其值与第一分压电阻器的电阻成固定关系，并且产生取决于从另一电阻器导出的值的电压。电压和部分电压被馈送到比较器，用于将比较结果输出到下游控制逻辑单元，该逻辑单元耦合到第一分压器的电阻器，并根据比较器输出信号产生控制信号。控制逻辑单元控制信号用于设置可变电阻，直到馈送到比较器的电压彼此相对应。

8. 发明授权

US08782458B2 System and method of data communications between electronic devices 有权
标题翻译：电子设备之间数据通信的系统和方法
公开(公告)号：US08782458B2
公开(公告)日：2014-07-15
申请号：US13306680
申请日：2011-11-29
申请人： Aaron Nygren , Anwar Kashem , Edoardo Prete , Gerry Talbot
发明人： Aaron Nygren , Anwar Kashem , Edoardo Prete , Gerry Talbot
IPC分类号： G06F1/00 , G11C7/00
CPC分类号： G06F13/4243
摘要： A system and method of data communications between a first device and a second device is disclosed. The method includes generating a first clock signal at the first device and generating a second clock signal having a phase offset from the first clock signal. The clock signals are transmitted from the first device to the second device. The method further includes regulating transmission of a read strobe signal sent from the second device to the first device utilizing the first clock signal. The method also includes regulating transmission of a data transfer signal sent from the second device to the first device utilizing the second clock signal.
摘要翻译：公开了第一设备和第二设备之间的数据通信的系统和方法。该方法包括在第一设备处产生第一时钟信号并产生具有与第一时钟信号相位偏移的第二时钟信号。时钟信号从第一设备发送到第二设备。该方法还包括利用第一时钟信号来调节从第二设备发送到第一设备的读选通信号的传输。该方法还包括利用第二时钟信号调节从第二设备发送到第一设备的数据传送信号的传输。

9. 发明申请

US20060214709A1 Circuit arrangement for generating a synchronization signal 审中-公开
标题翻译：用于产生同步信号的电路装置
公开(公告)号：US20060214709A1
公开(公告)日：2006-09-28
申请号：US11375569
申请日：2006-03-15
申请人： Aaron Nygren , Patrick Heyne
发明人： Aaron Nygren , Patrick Heyne
IPC分类号： H03L7/06
CPC分类号： H04L7/0337
摘要： A circuit arrangement is provided for generating a synchronization signal having signal edge changes whose timings are defined. The arrangement includes a plurality of controllable signal delay arrangements, each including a circuit part with variable signal delay and a circuit part with constant signal delay, where an input signal is supplied to a first controllable signal delay arrangement, a phase detection device including two inputs and one output, and a control circuit that controls the circuit parts with variable signal delay. The input of the control circuit is connected to the output of the phase detection device, and the output of the control circuit is connected to control inputs of the circuit parts with variable signal delay. The input signal is also supplied to the first input of the phase detection device. One output of one of the controllable signal delay arrangements is connected to the second input of the phase detection device. At least one of the controllable signal delay arrangements produces a synchronization signal at the output of the circuit part with variable signal delay.
摘要翻译：提供了一种电路装置，用于产生具有定义其定时的信号沿变化的同步信号。该装置包括多个可控信号延迟装置，每个可控信号延迟装置包括具有可变信号延迟的电路部分和具有恒定信号延迟的电路部分，其中输入信号被提供给第一可控信号延迟装置，相位检测装置包括两个输入和一个输出，以及控制电路，其具有可变的信号延迟。控制电路的输入端连接到相位检测装置的输出端，控制电路的输出端与可变信号延迟的电路部分的控制输入相连。输入信号也被提供给相位检测装置的第一输入端。可控信号延迟装置之一的一个输出端连接到相位检测装置的第二输入端。可控信号延迟装置中的至少一个在具有可变信号延迟的电路部分的输出处产生同步信号。

10. 发明申请

US20050253256A1 Supply line arrangement, off chip driver arrangement, and semiconductor circuitry module 审中-公开
标题翻译：电源线布置，芯片外驱动器布置和半导体电路模块
公开(公告)号：US20050253256A1
公开(公告)日：2005-11-17
申请号：US10835389
申请日：2004-04-30
申请人： Aaron Nygren
发明人： Aaron Nygren
IPC分类号： H01L23/522 , H01L23/58 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00346 , H03K19/0175
摘要： A supply line arrangement is provided wherein cutting means are provided which are adapted in order to subdivide and electrically insulate subsets or groups of provided off chip drivers with respect to each other wherein said cutting means are provided within internal first and second supply lines for internally supplying power or signals to the plurality of off chip drivers.
摘要翻译：提供了一种供应线布置，其中提供了切割装置，其切割装置适于相对于彼此细分和电绝缘提供的切片驱动器的子集或组，其中所述切割装置设置在内部第一和第二供应管线内部供内部供应电源或信号到多个芯片外驱动器。

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