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51. 发明授权

US08566827B2 System and method of arbitrating access of threads to shared resources within a data processing system 有权
标题翻译：线程访问数据处理系统内共享资源的系统和方法
公开(公告)号：US08566827B2
公开(公告)日：2013-10-22
申请号：US11260611
申请日：2005-10-27
申请人： Greg R. Mewhinney , Mysore S. Srinivas
发明人： Greg R. Mewhinney , Mysore S. Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/526 , G06F9/485
摘要： A first collection of threads which represent a collection of tasks to be executed by at least one of a collection of processing units is monitored. In response to detecting a request by a thread among the first collection of threads to access a shared resource locked by a second thread among the collection of threads, the first thread attempts to access a list associated with the shared resource. The list orders at least one thread among the collection of threads by priority of access to the shared resource. In response to determining the list is locked by a third thread among the collection of threads, the first thread is placed into a sleep state to be reawakened in a fixed period of time. In response to determining that at least one of the collection of processing units has entered into an idle state, the first thread is awakened from the sleep state before the fixed period of time has expired. Also, in response to awakening the first thread from the sleep state, the first thread is assigned to at least one of the collection of processing units and the first thread retries its attempt to access the list.
摘要翻译：监视表示要由处理单元的集合中的至少一个执行的任务的集合的线程的第一集合。响应于在线程的第一集合中检测到线程的请求以访问由线程集合中的第二线程锁定的共享资源的请求，则第一线程尝试访问与共享资源相关联的列表。该列表通过访问共享资源的优先级来排序线程集合中的至少一个线程。响应于确定列表被线程集合中的第三线程锁定，第一线程被置于休眠状态以在固定的时间段内被重新唤醒。响应于确定处理单元的集合中的至少一个已经进入空闲状态，在固定时间段到期之前，第一线程从睡眠状态唤醒。而且，响应于将第一线程从睡眠状态唤醒，第一线程被分配给处理单元集合中的至少一个，并且第一线程重试其访问列表的尝试。

52. 发明申请

US20120180052A1 Application Performance with Support for Re-Initiating Unconfirmed Software-Initiated Threads in Hardware 失效
标题翻译：支持应用程序性能，支持在硬件中重新启动未经确认的软件启动的线程
公开(公告)号：US20120180052A1
公开(公告)日：2012-07-12
申请号：US13427045
申请日：2012-03-22
申请人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Matthew Accapadi , Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/455
CPC分类号： G06F9/505 , G06F12/0862 , G06F2209/503 , G06F2212/6026
摘要： A method, system and computer-usable medium are disclosed for managing prefetch streams in a virtual machine environment. Compiled application code in a first core, which comprises a Special Purpose Register (SPR) and a plurality of first prefetch engines, initiates a prefetch stream request. If the prefetch stream request cannot be initiated due to unavailability of a first prefetch engine, then an indicator bit indicating a Prefetch Stream Dispatch Fault is set in the SPR, causing a Hypervisor to interrupt the execution of the prefetch stream request. The Hypervisor then calls its associated operating system (OS), which determines prefetch engine availability for a second core comprising a plurality of second prefetch engines. If a second prefetch engine is available, then the OS migrates the prefetch stream request from the first core to the second core, where it is initiated on an available second prefetch engine.
摘要翻译：公开了用于管理虚拟机环境中的预取流的方法，系统和计算机可用介质。包括专用寄存器（SPR）和多个第一预取引擎的第一核心中的编译应用代码启动预取流请求。如果由于第一预取引擎不可用而不能启动预取流请求，则在SPR中设置指示预取流调度故障的指示符位，导致管理程序中断预取流请求的执行。管理程序然后调用其关联的操作系统（OS），其确定包括多个第二预取引擎的第二核心的预取引擎可用性。如果第二预取引擎可用，则OS将预取流请求从第一核心迁移到第二核心，其中它在可用的第二预取引擎上启动。

53. 发明申请

US20120096241A1 Performance of Emerging Applications in a Virtualized Environment Using Transient Instruction Streams 有权
公开(公告)号：US20120096241A1
公开(公告)日：2012-04-19
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, JR. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.

54. 发明授权

US09323527B2 Performance of emerging applications in a virtualized environment using transient instruction streams 有权
标题翻译：使用瞬态指令流在虚拟化环境中的新兴应用程序的性能
公开(公告)号：US09323527B2
公开(公告)日：2016-04-26
申请号：US12905208
申请日：2010-10-15
申请人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
发明人： Robert H. Bell, Jr. , Hong L. Hua , Ram Raghavan , Mysore S. Srinivas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30054 , G06F9/30185 , G06F9/3802
摘要： A method, system and computer-usable medium are disclosed for managing transient instruction streams. Transient flags are defined in Branch-and-Link (BRL) instructions that are known to be infrequently executed. A bit is likewise set in a Special Purpose Register (SPR) of the hardware (e.g., a core) that is executing an instruction request thread. Subsequent fetches or prefetches in the request thread are treated as transient and are not written to lower-level caches. If an instruction is non-transient, and if a lower-level cache is non-inclusive of the L1 instruction cache, a fetch or prefetch miss that is obtained from memory may be written in both the L1 and the lower-level cache. If it is not inclusive, a cast-out from the L1 instruction cache may be written in the lower-level cache.
摘要翻译：公开了用于管理瞬时指令流的方法，系统和计算机可用介质。在已知很少执行的分支和链路（BRL）指令中定义了瞬态标志。在执行指令请求线程的硬件（例如，核心）的专用寄存器（SPR）中同样设置一个位。请求线程中的后续提取或预取将被视为暂时的，并且不会写入低级缓存。如果指令是非瞬态的，并且如果低级缓存不包括L1指令高速缓存，则从存储器获得的获取或预取缺失可以被写入L1和下级高速缓存中。如果不包括在内，则可以将低速缓存中的L1指令高速缓存中的退出写入。

55. 发明授权

US08490094B2 Non-uniform memory access (NUMA) enhancements for shared logical partitions 失效
标题翻译：共享逻辑分区的非均匀内存访问（NUMA）增强功能
公开(公告)号：US08490094B2
公开(公告)日：2013-07-16
申请号：US12394669
申请日：2009-02-27
申请人： Vaijayanthimala K. Anand , Mark R. Funk , Steven R. Kunkel , Mysore S. Srinivas , Randal C. Swanberg , Ronald D. Young
发明人： Vaijayanthimala K. Anand , Mark R. Funk , Steven R. Kunkel , Mysore S. Srinivas , Randal C. Swanberg , Ronald D. Young
IPC分类号： G06F9/50 , G06F13/00
CPC分类号： G06F9/5077 , G06F2212/2542
摘要： In a NUMA-topology computer system that includes multiple nodes and multiple logical partitions, some of which may be dedicated and others of which are shared, NUMA optimizations are enabled in shared logical partitions. This is done by specifying a home node parameter in each virtual processor assigned to a logical partition. When a task is created by an operating system in a shared logical partition, a home node is assigned to the task, and the operating system attempts to assign the task to a virtual processor that has a home node that matches the home node for the task. The partition manager then attempts to assign virtual processors to their corresponding home nodes. If this can be done, NUMA optimizations may be performed without the risk of reducing the performance of the shared logical partition.
摘要翻译：在包含多个节点和多个逻辑分区的NUMA拓扑计算机系统中，其中一些可能是专用的，其他的可以是共享的，而在共享逻辑分区中启用了NUMA优化。这是通过在分配给逻辑分区的每个虚拟处理器中指定家庭节点参数来完成的。当由共享逻辑分区中的操作系统创建任务时，将家庭节点分配给该任务，并且操作系统尝试将该任务分配给具有与该任务的家庭节点匹配的家庭节点的虚拟处理器。然后，分区管理器尝试将虚拟处理器分配给其对应的家庭节点。如果可以这样做，可以执行NUMA优化，而不会降低共享逻辑分区的性能。

56. 发明授权

US08230430B2 Scheduling threads in a multiprocessor computer 失效
标题翻译：在多处理器计算机中调度线程
公开(公告)号：US08230430B2
公开(公告)日：2012-07-24
申请号：US12059461
申请日：2008-03-31
申请人： Jos M. Accapadi , Matthew Accapadi , Andrew Dunshea , Mark E. Hack , Agustin Mena , Mysore S. Srinivas
发明人： Jos M. Accapadi , Matthew Accapadi , Andrew Dunshea , Mark E. Hack , Agustin Mena , Mysore S. Srinivas
IPC分类号： G06F9/46 , G06F13/24
CPC分类号： G06F9/5027 , G06F9/4812
摘要： Methods, systems, and computer program products are provided for scheduling threads in a multiprocessor computer. Embodiments include selecting a thread in a ready queue to be dispatched to a processor and determining whether an interrupt mask flag is set in a thread control block associated with the thread. If the interrupt mask flag is set in the thread control block associated with the thread, embodiments typically include selecting a processor, setting a current processor priority register of the selected processor to least favored, and dispatching the thread from the ready queue to the selected processor. In some embodiments, setting the current processor priority register of the selected processor to least favored is carried out by storing a value associated with the highest interrupt priority in the current processor priority register.
摘要翻译：提供方法，系统和计算机程序产品用于在多处理器计算机中调度线程。实施例包括选择要发送到处理器的准备队列中的线程，并且确定是否在与线程相关联的线程控制块中设置了中断屏蔽标志。如果在与线程相关联的线程控制块中设置中断屏蔽标志，则实施例通常包括选择处理器，将所选择的处理器的当前处理器优先级寄存器设置为最不利，并将线程从就绪队列调度到所选择的处理器。在一些实施例中，将所选择的处理器的当前处理器优先级寄存器设置为最不利的是通过在当前处理器优先级寄存器中存储与最高中断优先级相关联的值来执行。

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