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51. 发明授权

US07795940B2 Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures 失效
标题翻译：微相调节和微相调谐混频器电路采用标准场效应晶体管结构设计
公开(公告)号：US07795940B2
公开(公告)日：2010-09-14
申请号：US12573910
申请日：2009-10-06
申请人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
发明人： Wagdi W. Abadeer , Anthony R. Bonaccio , Joseph A. Iadanza
IPC分类号： H03K3/00 , H03H11/16 , H03K5/13
CPC分类号： H03K5/06 , H03K2005/00052 , H03K2005/00058
摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
摘要翻译：这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。这些电路包括连接在输入和输出节点之间的可变延迟器件。该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过门和输出扩散区域并联连接到输出节点。当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

52. 发明授权

US07716007B2 Design structures of powering on integrated circuit 失效
标题翻译：集成电路供电的设计结构
公开(公告)号：US07716007B2
公开(公告)日：2010-05-11
申请号：US12163025
申请日：2008-06-27
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G01K1/08 , G06F11/00
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

53. 发明授权

US07573937B2 Phase rotator control test scheme 失效
标题翻译：相转子控制试验方案
公开(公告)号：US07573937B2
公开(公告)日：2009-08-11
申请号：US11155027
申请日：2005-06-16
申请人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer , Daniel G. Young
发明人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer , Daniel G. Young
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： G01R31/317
摘要： Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degree rotation). Each operational phase rotator should respond with an equal but opposite phase shift in order to maintain phase lock. Thus, after sweeping, each tap weight is exercised, which may help ensure defective tap weights in any (e.g., quadrant) are detected during testing.
摘要翻译：提供了用于检测有缺陷抽头重量的相位旋转器的技术和装置。相位旋转器测试逻辑可以包括主相位旋转器，以通过整个相位周期（例如，整个360度旋转）来循环分配到操作相位旋转器的时钟信号的相位。每个操作相位旋转器应以相等但相反的相移进行响应，以保持锁相。因此，在清扫之后，执行每个抽头重量，这有助于确保在测试期间检测到任何（例如象限）中的有缺陷的抽头重量。

54. 发明授权

US07483806B1 Design structures, method and systems of powering on integrated circuit 失效
标题翻译：集成电路供电的设计结构，方法和系统
公开(公告)号：US07483806B1
公开(公告)日：2009-01-27
申请号：US11866537
申请日：2007-10-03
申请人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
发明人： Igor Arsovski , Anthony R. Bonaccio , Serafino Bueti , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Hemen R. Shah , Pradeep Thiagarajan , Sebastian T. Ventrone
IPC分类号： G06F15/00 , G06F11/00
CPC分类号： G06F1/206 , Y02D10/16 , Y10T307/773
摘要： Design structures, method and systems of powering on an integrated circuit (IC) are disclosed. In one embodiment, the system includes a region in the IC including functional logic, a temperature sensor for sensing a temperature in the region when the IC is powered up and a heating element therefor; a processing unit including: a comparator for comparing the temperature against a predetermined temperature value, a controller, which in the case that the temperature is below the predetermined temperature value, delays functional operation of the IC and controls heating of the region of the IC, and a monitor for monitoring the temperature in the region; and wherein the controller, in the case that the temperature rises above the predetermined temperature value, ceases the heating and initiates functional operation of the IC.
摘要翻译：公开了对集成电路（IC）供电的设计结构，方法和系统。在一个实施例中，该系统包括IC中的包括功能逻辑的区域，用于感测IC上电时该区域中的温度的温度传感器及其加热元件; 处理单元，包括：用于将温度与预定温度值进行比较的比较器，在温度低于预定温度值的情况下的控制器，延迟IC的功能操作并控制IC的区域的加热，以及监测该区域的温度的监测器; 并且其中所述控制器在所述温度升高到所述预定温度值以上的情况下停止所述加热并且启动所述IC的功能操作。

55. 发明授权

US07449942B2 Intrinsic RC power distribution for noise filtering of analog supplies 有权
标题翻译：用于模拟电源噪声滤波的本征RC功率分配
公开(公告)号：US07449942B2
公开(公告)日：2008-11-11
申请号：US11276451
申请日：2006-02-28
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Sebastian T. Ventrone , Stephen D. Wyatt
IPC分类号： H03K5/00
CPC分类号： G05F1/46
摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.
摘要翻译：用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

56. 发明授权

US07053712B2 Method and apparatus for controlling common-mode output voltage in fully differential amplifiers 有权
标题翻译：用于控制全差分放大器中共模输出电压的方法和装置
公开(公告)号：US07053712B2
公开(公告)日：2006-05-30
申请号：US10710745
申请日：2004-07-30
申请人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Michael A. Sorna , Sebastian T. Ventrone
发明人： Anthony R. Bonaccio , Hayden C. Cranford, Jr. , Michael A. Sorna , Sebastian T. Ventrone
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/78 , H03F2203/45418 , H03F2203/45424 , H03F2203/45521
摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.
摘要翻译：一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压和参考电压。误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。

57. 发明授权

US06452448B1 Family of analog amplifier and comparator circuits with body voltage control 有权
标题翻译：具有体电压控制的模拟放大器和比较器电路系列
公开(公告)号：US06452448B1
公开(公告)日：2002-09-17
申请号：US09616550
申请日：2000-07-14
申请人： Anthony R. Bonaccio , Michel S. Michail , Wilbur D. Pricer , Steven J. Tanghe
发明人： Anthony R. Bonaccio , Michel S. Michail , Wilbur D. Pricer , Steven J. Tanghe
IPC分类号： H03F345
CPC分类号： H03F3/45748 , H03F3/4521 , H03F2203/45342 , H03F2203/45658 , H03F2203/45711
摘要： A structure for an amplifier circuit which includes a pair of source-coupled differential transistors, each of source-coupled differential transistors having a body and a gate, and input transistors electrically connected to the source-coupled transistors. Also, the input transistors load the body and the gate of the source-coupled transistors with positive feedback signals. As a result, a differential gain is increased and a common mode gain is not increased. The output of the pair of source-coupled differential transistors is directed to second pair of transistors. The second pair of transistors generates mirrored voltages which track with input voltages. The second pair of transistors generates mirrored voltages translated by an offset voltage to values near ground, mirrored voltages which represent a voltage gain over an input voltage, and mirrored voltages which are largely differential and includes approximately no common mode input voltage.
摘要翻译：一种用于放大器电路的结构，其包括一对源极耦合差分晶体管，每个源极耦合差分晶体管具有主体和栅极，以及输入晶体管，电连接到源耦合晶体管。此外，输入晶体管负载负极反馈信号的源极耦合晶体管的主体和栅极。结果，差分增益增加并且共模增益不增加。一对源极耦合差分晶体管的输出被引导到第二对晶体管。第二对晶体管产生用输入电压跟踪的镜像电压。第二对晶体管产生由偏移电压转换为接近接近的值的镜像电压，表示输入电压上的电压增益的镜像电压和大幅度差分的近似不包含共模输入电压的镜像电压。

58. 发明授权

US06337573B1 Contact test circuit 失效
标题翻译：接触测试电路
公开(公告)号：US06337573B1
公开(公告)日：2002-01-08
申请号：US09360150
申请日：1999-07-26
申请人： Anthony R. Bonaccio , Howard J. Leighton
发明人： Anthony R. Bonaccio , Howard J. Leighton
IPC分类号： G01R1073
CPC分类号： G01R31/043
摘要： A method and apparatus for contact testing a plurality of devices under test, either sequentially or simultaneously. In a first test phase it is determined whether the test probe to each contact is shorted to the most negative rail. In a second phase it is determined whether the test probe has made proper contact, and whether ESD diodes on the devices under test are functional. In both test phases a negative pulse is generated on a tester bus and applied to the contact by the test probe. In the first test phase the positive rail of the device under test is grounded; in the second test phase the positive rail of the device under test is made positive. The negative rail of the device under test is connected to the negative rail of the tester. In both test phases, upon termination of the negative pulse, the bus is restored to a positive voltage which is dependent upon the condition of the contact and the condition of expected input devices at the contact. The bus voltage is measured in accordance with a logic which determines the condition of the contact and the condition of expected input devices at the contact. Data signals for functional testing of the device under test are can be applied to the bus through an isolating driver which preserves the logic of the contact test.
摘要翻译：一种用于连续或同时接触测试多个待测器件的方法和装置。在第一个测试阶段，确定每个触点的测试探针是否短接到最负的导轨。在第二阶段，确定测试探针是否已正确接触，以及被测器件上的ESD二极管是否正常工作。在两个测试阶段，在测试仪总线上产生负脉冲，并通过测试探头施加到触点。在第一个测试阶段，被测器件的正极接地; 在第二个测试阶段，正在测试的器件的正极。被测器件的负极线连接到测试仪的负极轨。在两个测试阶段，在负脉冲终止时，总线恢复到正电压，这取决于触点的状态和触点处的预期输入设备的状态。总线电压根据确定触点状态的逻辑和触点处的预期输入装置的状态来测量。用于测试设备功能测试的数据信号可以通过保护接触测试逻辑的隔离驱动器应用于总线。

59. 发明授权

US5424662A Differential current mode driver circuit with low common-mode noise 失效
标题翻译：差分电流模式驱动电路具有低共模噪声
公开(公告)号：US5424662A
公开(公告)日：1995-06-13
申请号：US250968
申请日：1994-05-31
申请人： Anthony R. Bonaccio
发明人： Anthony R. Bonaccio
IPC分类号： H03K19/018 , H04L25/02 , G01R19/00
CPC分类号： H04L25/0282 , H03K19/01831 , H04L25/0274
摘要： An improved, differential current-mode driver circuit with low common-mode noise and high output impedance. In this circuit both sink and source currents are controlled by two pairs of emitter coupled differential amplifiers operated as current switches. One of the pairs of current switches is comprised of PNP transistors and hence slower than the other pair of current switches which is comprises of NPN transistors. The input data is applied differentially to the slower pair of the current switches and simultaneously to auxiliary switches which act as inverting amplifiers and are cross-coupled to and drive the inputs of the two faster current switches. A fifth current switch and auxiliary switch inverting amplifier is used to as an inhibit circuit to shunt both source and sink currents to ground so that no circuit node will swing excessively while holding the output nodes of the current sink and source a constant voltage thus reducing common-mode noise.
摘要翻译：具有低共模噪声和高输出阻抗的改进的差分电流模式驱动电路。在这个电路中，电流和源极电流由两对发射极耦合差动放大器控制，作为电流开关。一对电流开关由PNP晶体管组成，因此比由NPN晶体管组成的另一对电流开关慢。输入数据差分地施加到较慢的电流开关对，并同时用于辅助开关，这些辅助开关用作反相放大器，并且交叉耦合到并驱动两个更快的电流开关的输入。第五个电流开关和辅助开关反相放大器被用作抑制电路，以将源电流和吸收电流分流到地，使得没有电路节点过度摆动，同时保持电流吸收器的输出节点并且源极具有恒定的电压，从而减少常见的模式噪音

60. 发明授权

US08587464B2 Off-line gain calibration in a time-interleaved analog-to-digital converter 有权
标题翻译：时间交错模数转换器中的离线增益校准
公开(公告)号：US08587464B2
公开(公告)日：2013-11-19
申请号：US13346242
申请日：2012-01-09
申请人： Anthony R. Bonaccio , Frank R. Keyser, III , Martin L. Schmatz , Benjamin T. Voegli
发明人： Anthony R. Bonaccio , Frank R. Keyser, III , Martin L. Schmatz , Benjamin T. Voegli
IPC分类号： H03M1/12
CPC分类号： H03M1/182 , H03M1/1215
摘要： A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADC blocks each including: at least one ADC unit configured to convert an analog input to a digital output; and a digital gain controller configured to adjust a reference voltage of the at least one ADC unit based on a comparison of an actual output of the at least one ADC unit to an expected output of the at least one ADC unit.
摘要翻译：时间交织的模数转换器（ADC）包括多个ADC块，每个ADC块包括：至少一个ADC单元，被配置为将模拟输入转换成数字输出; 以及数字增益控制器，被配置为基于所述至少一个ADC单元的实际输出与所述至少一个ADC单元的预期输出的比较来调整所述至少一个ADC单元的参考电压。

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