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1. 发明授权

US07573937B2 Phase rotator control test scheme 失效
标题翻译：相转子控制试验方案
公开(公告)号：US07573937B2
公开(公告)日：2009-08-11
申请号：US11155027
申请日：2005-06-16
申请人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer , Daniel G. Young
发明人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer , Daniel G. Young
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： G01R31/317
摘要： Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degree rotation). Each operational phase rotator should respond with an equal but opposite phase shift in order to maintain phase lock. Thus, after sweeping, each tap weight is exercised, which may help ensure defective tap weights in any (e.g., quadrant) are detected during testing.
摘要翻译：提供了用于检测有缺陷抽头重量的相位旋转器的技术和装置。相位旋转器测试逻辑可以包括主相位旋转器，以通过整个相位周期（例如，整个360度旋转）来循环分配到操作相位旋转器的时钟信号的相位。每个操作相位旋转器应以相等但相反的相移进行响应，以保持锁相。因此，在清扫之后，执行每个抽头重量，这有助于确保在测试期间检测到任何（例如象限）中的有缺陷的抽头重量。

2. 发明申请

US20080069278A1 Asynchronous Phase Rotator Control 审中-公开
标题翻译：异步相位转子控制
公开(公告)号：US20080069278A1
公开(公告)日：2008-03-20
申请号：US11533105
申请日：2006-09-19
申请人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer
发明人： Steven J. Baumgartner , Anthony R. Bonaccio , Timothy C. Buchholtz , Charles P. Geer
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： The present invention generally relates to centering a clock edge at or near the center of a data eye. Data may be sent from a first device to a second device in conjunction with a clock signal. A phase rotator operating in an external clock domain governed by the clock signal received at the second device may rotate the phase of the received clock signal to sample data. The data sampled in the unstable external clock domain may be transferred to a stable local clock domain for analysis. Feedback may be provided from the stable clock domain to the phase rotator to adjust the phase of the received clock signal to position an edge of the clock signal at or near the center of the data eye.
摘要翻译：本发明一般地涉及使数据眼的中心处或附近的时钟沿居中。数据可以与时钟信号一起从第一设备发送到第二设备。在由在第二设备处接收的时钟信号控制的外部时钟域中工作的相位旋转器可将接收的时钟信号的相位旋转为采样数据。在不稳定的外部时钟域中采样的数据可能被传送到稳定的本地时钟域进行分析。可以从稳定时钟域向相位旋转器提供反馈以调整接收的时钟信号的相位，以将时钟信号的边沿定位在数据眼的中心处或附近。

3. 发明授权

US07940878B2 Unlock mode in source synchronous receivers 失效
标题翻译：源同步接收器中的解锁模式
公开(公告)号：US07940878B2
公开(公告)日：2011-05-10
申请号：US11678256
申请日：2007-02-23
申请人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
发明人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
IPC分类号： H03D3/24 , H04L7/00
CPC分类号： H03L7/0812 , H04L7/0008
摘要： A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
摘要翻译：锁相环产生对应于源同步输入和输入链路时钟信号的输出。相位锁定反馈系统接收输入和输入链路时钟信号，并检测输出和输入之间的相位偏差。相位锁定反馈系统还基于相位偏差来调整调整的时钟信号，从而使相位锁定反馈系统产生输出，使得输出与输入具有稳定的相位关系。第一机制使得相位锁定反馈系统在出现第一预定义事件时不跟踪输出和输入之间的相位偏差，从而将经调整的时钟信号保持在当前状态。

4. 发明申请

US20080205570A1 Unlock Mode in Source Synchronous Receivers 失效
标题翻译：源同步接收机中的解锁模式
公开(公告)号：US20080205570A1
公开(公告)日：2008-08-28
申请号：US11678256
申请日：2007-02-23
申请人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
发明人： Steven J. Baumgartner , Timothy C. Buchholtz , Andrew D. Davies , Thomas W. Liang , Andrew B. Maki , Thomas Pham , Dana M. Woeste , Daniel G. Young
IPC分类号： H03D3/24
CPC分类号： H03L7/0812 , H04L7/0008
摘要： A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
摘要翻译：锁相环产生对应于源同步输入和输入链路时钟信号的输出。相位锁定反馈系统接收输入和输入链路时钟信号，并检测输出和输入之间的相位偏差。相位锁定反馈系统还基于相位偏差来调整调整的时钟信号，从而使相位锁定反馈系统产生输出，使得输出与输入具有稳定的相位关系。第一机制使得相位锁定反馈系统在出现第一预定义事件时不跟踪输出和输入之间的相位偏差，从而将经调整的时钟信号保持在当前状态。

5. 发明授权

US4942399A Adaptive flash analog/digital converter for differential input signal 失效
标题翻译：用于差分输入信号的自适应闪存模拟/数字转换器
公开(公告)号：US4942399A
公开(公告)日：1990-07-17
申请号：US324267
申请日：1989-03-15
申请人： Timothy C. Buchholtz , Michael R. Gruver , Raymond A. Richetta , Timothy J. Schmerbeck
发明人： Timothy C. Buchholtz , Michael R. Gruver , Raymond A. Richetta , Timothy J. Schmerbeck
IPC分类号： H03M1/36 , H03M1/12
CPC分类号： H03M1/129 , H03M1/365
摘要： A differential analog input signal is level-shifted and converted to single-ended form. Its average value is compared to the midpoint of a set of reference voltages. A control signal proportional to the average value forces the average of the single-ended signal toward the midpoint voltage. The single-ended signal is converted to uncoded digital form by a parallel comparator bank, and is then converted to coded digital form.

6. 发明授权

US5355030A Low voltage BICMOS logic switching circuit 失效
标题翻译：低电压BICMOS逻辑开关电路
公开(公告)号：US5355030A
公开(公告)日：1994-10-11
申请号：US985990
申请日：1992-12-04
申请人： Timothy C. Buchholtz , Nghia Van Phan , Michael J. Rohn
发明人： Timothy C. Buchholtz , Nghia Van Phan , Michael J. Rohn
IPC分类号： H03K19/01 , H03K19/017 , H03K19/08 , H03K19/0944 , H03K19/082 , H03K19/0948
CPC分类号： H03K19/09448 , H03K19/01721
摘要： The present invention involves a BICMOS logic switching circuit biased between upper and lower supply voltages. This circuit includes a CMOS logic circuit driven by a plurality of logic input signals. This logic switching circuit also has a driving circuit coupled to the CMOS logic switching circuit and includes an output node, a first bipolar transistor, and a second bipolar transistor. The first bipolar transistor is coupled in series with the second bipolar transistor with the output node therebetween for providing an output signal on the output node, wherein the second bipolar transistor has a base directly coupled to a field effect transistor switch coupled to the upper supply voltage. The field effect transistor switch is controlled by logic input signals. The circuit also includes a switching circuit coupled to the upper supply voltage, the lower supply voltage, and the output node for causing the output signal on the output node to swing fully between the upper and the lower supply voltages in response to changes in the logic input signals.
摘要翻译：本发明涉及一种偏置在上下电源电压之间的BICMOS逻辑开关电路。该电路包括由多个逻辑输入信号驱动的CMOS逻辑电路。该逻辑开关电路还具有耦合到CMOS逻辑开关电路的驱动电路，并且包括输出节点，第一双极晶体管和第二双极晶体管。第一双极晶体管与第二双极晶体管串联耦合，其间具有输出节点，用于在输出节点上提供输出信号，其中第二双极晶体管具有直接耦合到耦合到较高电源电压的场效应晶体管开关的基极。场效应晶体管开关由逻辑输入信号控制。电路还包括耦合到上电源电压，较低电源电压和输出节点的开关电路，用于使得输出节点上的输出信号响应于逻辑上的变化而在上电源电压和下电源电压之间完全摆动输入信号。

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