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51. 发明授权

US6083849A Methods of forming hemispherical grain polysilicon 失效
标题翻译：形成半球状晶粒多晶硅的方法
公开(公告)号：US6083849A
公开(公告)日：2000-07-04
申请号：US18228
申请日：1998-02-03
申请人： Er-Xuan Ping , Li Li
发明人： Er-Xuan Ping , Li Li
IPC分类号： C09K13/06 , H01L21/02 , H01L21/306 , H01L21/302
CPC分类号： H01L21/02049 , C09K13/06 , H01L21/02063 , H01L21/02068 , H01L28/84
摘要： In one aspect, the invention encompasses a semiconductor processing method comprising contacting a surface with a liquid solution comprising at least one fluorine-containing species and a temperature of at least about 40.degree. C. In another aspect, the invention encompasses a method of passivating a silicon-comprising layer comprising contacting the layer with a liquid solution comprising hydrogen fluoride and a temperature of at least about 40.degree. C. In yet another aspect, the invention encompasses a method of forming hemispherical grain polysilicon comprising: a) forming a layer comprising substantially amorphous silicon over a substrate; b) contacting the layer comprising substantially amorphous silicon with a liquid solution comprising fluorine-containing species and a temperature of at least about 40.degree. C.; c) seeding the layer comprising substantially amorphous silicon; and d) annealing the seeded layer to convert at least a portion of the seeded layer to hemispherical grain polysilicon.
摘要翻译：一方面，本发明包括一种半导体处理方法，其包括将表面与包含至少一种含氟物质的液体溶液和至少约40℃的温度接触。另一方面，本发明包括一种钝化方法含硅层包括使该层与包含氟化氢的液体溶液接触并且至少约40℃的温度。在另一方面，本发明包括形成半球形晶粒多晶硅的方法，包括：a）形成包括基本上非晶硅; b）使包含基本上非晶硅的层与包含含氟物质的液体溶液和至少约40℃的温度接触; c）将包含基本上非晶硅的层接种; 以及d）退火所述接种层以将所述接种层的至少一部分转化为半球形晶粒多晶硅。

52. 发明授权

US6015997A Semiconductor structure having a doped conductive layer 失效
公开(公告)号：US6015997A
公开(公告)日：2000-01-18
申请号：US803174
申请日：1997-02-19
申请人： Yongjun Hu , Pai-Hung Pan , Er-Xuan Ping , Randhir P.S. Thakur , Scott DeBoer
发明人： Yongjun Hu , Pai-Hung Pan , Er-Xuan Ping , Randhir P.S. Thakur , Scott DeBoer
IPC分类号： H01L21/28 , H01L29/49 , H01L29/76 , H01L29/74 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28044 , H01L21/28052 , H01L29/4941
摘要： Methods and apparatus for forming word line stacks comprise one, or a combination of the following: a silicon diffusion barrier layer, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer; an amorphous silicon diffusion barrier coupled between a polysilicon layer and a conductor layer; a thin nitride layer coupled between a bottom silicon layer and a titanium silicide conductor layer, and a bottom silicon layer coupled to a conductor layer, which comprises C54-titanium silicide. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

53. 发明授权

US09530674B2 Method and system for three-dimensional (3D) structure fill 有权
标题翻译：三维（3D）结构填充的方法和系统
公开(公告)号：US09530674B2
公开(公告)日：2016-12-27
申请号：US14044138
申请日：2013-10-02
申请人： Ellie Yieh , Ludovic Godet , Srinivas Nemani , Er-Xuan Ping , Gary Dickerson
发明人： Ellie Yieh , Ludovic Godet , Srinivas Nemani , Er-Xuan Ping , Gary Dickerson
IPC分类号： H01L21/00 , H01L21/67 , C23C14/02 , C23C14/04 , C23C16/02 , C23C16/04 , H01L21/02
CPC分类号： H01L21/02271 , C23C14/021 , C23C14/046 , C23C16/0227 , C23C16/045 , C23C16/45544 , C23C16/50 , H01J37/32009 , H01J2237/334 , H01L21/02266 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/2855 , H01L21/28556 , H01L21/31116 , H01L21/32136 , H01L21/67017 , H01L21/67213 , H01L21/76224
摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.
摘要翻译：实施例包括3D结构填充的方法和系统。在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。材料沉积在沟槽中。材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

54. 发明授权

US08866124B2 Diodes with native oxide regions for use in memory arrays and methods of forming the same 有权
标题翻译：具有用于存储器阵列的自然氧化物区域的二极管及其形成方法
公开(公告)号：US08866124B2
公开(公告)日：2014-10-21
申请号：US13020007
申请日：2011-02-02
申请人： Steven Maxwell , Abhijit Bandyopadhyay , Kun Hou , Er-Xuan Ping , Yung-Tin Chen , Li Xiao
发明人： Steven Maxwell , Abhijit Bandyopadhyay , Kun Hou , Er-Xuan Ping , Yung-Tin Chen , Li Xiao
IPC分类号： H01L47/00 , H01L29/868 , H01L27/102
CPC分类号： H01L27/1021 , H01L29/868 , Y10S438/90
摘要： In a first aspect, a vertical semiconductor diode is provided that includes (1) a first semiconductor layer formed above a substrate; (2) a second semiconductor layer formed above the first semiconductor layer; (3) a first native oxide layer formed above the first semiconductor layer; and (4) a third semiconductor layer formed above the first semiconductor layer, second semiconductor layer and first native oxide layer so as to form the vertical semiconductor diode that includes the first native oxide layer. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种垂直半导体二极管，其包括：（1）形成在基板上的第一半导体层; （2）形成在第一半导体层上方的第二半导体层; （3）形成在所述第一半导体层上方的第一自然氧化物层; 以及（4）形成在第一半导体层上的第三半导体层，第二半导体层和第一自然氧化物层，以形成包括第一自然氧化物层的垂直半导体二极管。提供了许多其他方面。

55. 发明申请

US20130320542A1 Method of fabricating a self-aligned buried bit line for a vertical channel dram 有权
标题翻译：制造垂直通道的自对准埋置位线的方法
公开(公告)号：US20130320542A1
公开(公告)日：2013-12-05
申请号：US13986499
申请日：2013-05-08
申请人： Chorng-Ping Chang , Bingxi Wood , Er-Xuan Ping
发明人： Chorng-Ping Chang , Bingxi Wood , Er-Xuan Ping
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/76889 , H01L21/743 , H01L23/498 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less.
摘要翻译：在构成垂直通道DRAM的一部分的结构中制造自对准埋入位线的方法。所使用的材料和工艺在制造过程中能够对掩埋位线的元件进行自对准。此外，所使用的材料和工艺能够形成具有16nm或更小的掩埋位线宽度的各个DRAM单元。

56. 发明授权

US08470646B2 Modulation of resistivity in carbon-based read-writeable materials 有权
标题翻译：碳基可读写材料中电阻率的调制
公开(公告)号：US08470646B2
公开(公告)日：2013-06-25
申请号：US12650417
申请日：2009-12-30
申请人： Huiwen Xu , Xiying Chen , Er-Xuan Ping
发明人： Huiwen Xu , Xiying Chen , Er-Xuan Ping
IPC分类号： H01L21/332 , H01L21/20 , H01L29/02 , H01L47/00
CPC分类号： G11C13/00 , G11C13/0004 , G11C2213/35 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/065 , H01L45/1233 , H01L45/149 , H01L45/1616
摘要： In a first aspect, a method of forming a memory cell is provided that includes (1) forming a metal-insulator-metal (“MIM”) stack above a substrate, the MIM stack including a carbon-based switching material having a resistivity of at least 1×104 ohm-cm; and (2) forming a steering element coupled to the MIM stack. Numerous other aspects are provided.
摘要翻译：在第一方面，提供一种形成存储单元的方法，其包括：（1）在衬底上形成金属 - 绝缘体 - 金属（“MIM”）堆叠，所述MIM堆叠包括具有电阻率的碳基开关材料至少1×104欧姆厘米; 和（2）形成耦合到所述MIM堆叠的操纵元件。提供了许多其他方面。

57. 发明授权

US08120124B2 Ultra thin TCS (SiCl4) cell nitride for DRAM capacitor with DCS (SiH2Cl2) interface seeding layer 失效
标题翻译：具有DCS（SiH2Cl2）界面接种层的DRAM电容器的超薄TCS（SiCl4）电池氮化物
公开(公告)号：US08120124B2
公开(公告)日：2012-02-21
申请号：US11712077
申请日：2007-02-28
申请人： Lingyi A. Zheng , Er-Xuan Ping
发明人： Lingyi A. Zheng , Er-Xuan Ping
IPC分类号： H01L21/00
CPC分类号： H01L21/0217 , C23C16/0272 , C23C16/345 , H01L21/02211 , H01L21/02271 , H01L21/31051 , H01L21/3115 , H01L21/3185 , H01L21/3211 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first exposed to a mixture of dichlorosilane (DCS) and a nitrogen-comprising gas to deposit a thin silicon nitride seeding layer on the surface, and then exposed to a mixture of silicon tetrachloride (TCS) and a nitrogen comprising gas to deposit a TCS silicon nitride layer on the DCS seeding layer. In another embodiment, the method involves first nitridizing the surface of the silicon-comprising substrate prior to forming the DCS nitride seeding layer and the TCS nitride layer. The method achieves a TCS nitride layer having a sufficient thickness to eliminate bubbling and punch-through problems and provide high electrical performance regardless of the substrate type. Also provided are methods of forming a capacitor, and the resulting capacitor structures.
摘要翻译：提供了一种在半导体器件上形成氮化硅膜的方法。在该方法的一个实施方案中，首先将含硅衬底暴露于二氯硅烷（DCS）和含氮气体的混合物以在表面上沉积薄氮化硅接种层，然后暴露于四氯化硅（TCS）和包含气体的氮气以在DCS籽晶层上沉积TCS氮化硅层。在另一个实施方案中，该方法包括在形成DCS氮化物接种层和TCS氮化物层之前首先氮化含硅衬底的表面。该方法实现了具有足够厚度的TCS氮化物层，以消除起泡和穿通问题，并且不管衬底类型如何，都能提供高电性能。还提供了形成电容器的方法以及所得到的电容器结构。

58. 发明授权

US08105867B2 Self-aligned three-dimensional non-volatile memory fabrication 有权
标题翻译：自对准三维非易失性存储器制造
公开(公告)号：US08105867B2
公开(公告)日：2012-01-31
申请号：US12468717
申请日：2009-05-19
申请人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
发明人： George Matamis , Henry Chien , James K Kai , Takashi Orimoto , Vinod R Purayath , Er-Xuan Ping , Roy E Scheuerlein
IPC分类号： H01L21/00
CPC分类号： H01L21/20 , G11C13/0004 , G11C17/16 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
摘要翻译：公开了一种用于三维非易失性存储器的自对准制造工艺。双重蚀刻工艺在与导体下面和上面的记忆柱自对准的给定水平处形成导体。以这种方式形成导体可以包括使用沿给定方向的第一重复图案蚀刻第一导体层以形成导体的第一部分。具有第一图案的蚀刻还限定了下面的柱结构的两个相对的侧壁，从而使导体与支柱自对准。蚀刻后，沉积第二导体层，随后沉积半导体层堆叠。执行以与第一图案相同的方向重复的第二图案的蚀刻，从而形成与上层叠层线自对准的导体的第二部分。然后将这些层堆叠线正交蚀刻以限定覆盖导体的第二组支柱。

59. 发明申请

US20110143538A1 Semiconductor Processing Methods 有权
标题翻译：半导体加工方法
公开(公告)号：US20110143538A1
公开(公告)日：2011-06-16
申请号：US13033268
申请日：2011-02-23
申请人： Junting Liu , Er-Xuan Ping , Seiichi Takedai
发明人： Junting Liu , Er-Xuan Ping , Seiichi Takedai
IPC分类号： H01L21/768
CPC分类号： H01L21/768 , C23C18/1605 , C25D5/022 , C25D7/12 , H01L21/56 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/03462 , H01L2224/03464 , H01L2224/03616 , H01L2224/0401 , H01L2224/04042 , H01L2224/056 , H01L2224/05664 , H01L2224/131 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/01028 , H01L2924/00
摘要： Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.
摘要翻译：一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

60. 发明申请

US20110095257A1 MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME 有权
标题翻译：包含基于碳的可逆电阻开关元件的存储器单元与转向元件兼容，以及形成其的方法
公开(公告)号：US20110095257A1
公开(公告)日：2011-04-28
申请号：US12834942
申请日：2010-07-13
申请人： Huiwen Xu , Er-Xuan Ping , Xiying Costa
发明人： Huiwen Xu , Er-Xuan Ping , Xiying Costa
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1675 , H01L21/02115 , H01L21/02274 , H01L21/3146 , H01L21/32139 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L45/1683
摘要： Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.
摘要翻译：提供了存储单元和形成这种存储单元的方法，其包括耦合到具有增加的电阻率的碳基可逆电阻率切换材料的转向元件和小于转向元件的最大电流能力的开关电流用于控制通过碳基可逆电阻率开关材料的电流。在特定实施例中，根据本发明的方法和装置形成具有第一宽度的转向元件，例如二极管，该第二宽度与第二宽度小于第一宽度的可逆电阻率开关材料（例如aC）耦合。

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