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1. 发明授权

US08867271B2 Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device 有权
标题翻译：层叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：US08867271B2
公开(公告)日：2014-10-21
申请号：US13484088
申请日：2012-05-30
申请人： Haibo Li , Xiying Costa , Masaaki Higashitani , Man L. Mui
发明人： Haibo Li , Xiying Costa , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

2. 发明授权

US08934292B2 Balanced method for programming multi-layer cell memories 有权
标题翻译：用于编程多层单元存储器的平衡方法
公开(公告)号：US08934292B2
公开(公告)日：2015-01-13
申请号：US13051885
申请日：2011-03-18
申请人： Xiying Costa , Yibo Nian , Roy Scheuerlein , Tz-Yi Liu , Chandrasekhar Reddy Gorla
发明人： Xiying Costa , Yibo Nian , Roy Scheuerlein , Tz-Yi Liu , Chandrasekhar Reddy Gorla
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2013/0076 , G11C2013/0092 , G11C2213/32
摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.
摘要翻译：改进的多级金属氧化物存储单元的编程方法平衡施加的电压和电流，以提供更好的性能。通过为编程中要实现的目标电阻状态确定适当的编程电压和电流限制，然后施加具有确定的设定电气特性的脉冲来实现将存储器单元转换到较低电阻状态的设置编程。将存储器单元转换到较高电阻状态的复位编程通过确定编程中要实现的状态的适当编程电压和可选的电流限制，然后施加具有确定的电特性的脉冲来实现。用于确定适当的设置或复位编程电压和电流值的算法提供有效的编程，而不会对存储元件造成影响。编程脉冲的电气特性可以存储在表查找算法中使用的数据表中。

3. 发明申请

US20130279257A1 Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current 有权
公开(公告)号：US20130279257A1
公开(公告)日：2013-10-24
申请号：US13450313
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

4. 发明申请

US20110095257A1 MEMORY CELL THAT INCLUDES A CARBON-BASED REVERSIBLE RESISTANCE SWITCHING ELEMENT COMPATIBLE WITH A STEERING ELEMENT, AND METHODS OF FORMING THE SAME 有权
标题翻译：包含基于碳的可逆电阻开关元件的存储器单元与转向元件兼容，以及形成其的方法
公开(公告)号：US20110095257A1
公开(公告)日：2011-04-28
申请号：US12834942
申请日：2010-07-13
申请人： Huiwen Xu , Er-Xuan Ping , Xiying Costa
发明人： Huiwen Xu , Er-Xuan Ping , Xiying Costa
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1675 , H01L21/02115 , H01L21/02274 , H01L21/3146 , H01L21/32139 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L45/1683
摘要： Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.
摘要翻译：提供了存储单元和形成这种存储单元的方法，其包括耦合到具有增加的电阻率的碳基可逆电阻率切换材料的转向元件和小于转向元件的最大电流能力的开关电流用于控制通过碳基可逆电阻率开关材料的电流。在特定实施例中，根据本发明的方法和装置形成具有第一宽度的转向元件，例如二极管，该第二宽度与第二宽度小于第一宽度的可逆电阻率开关材料（例如aC）耦合。

5. 发明授权

US08737111B2 Memory cell with resistance-switching layers 有权
标题翻译：具有电阻切换层的存储单元
公开(公告)号：US08737111B2
公开(公告)日：2014-05-27
申请号：US13157191
申请日：2011-06-09
申请人： Franz Kreupl , Xiying Costa , James Kai , Raghuveer S. Makala
发明人： Franz Kreupl , Xiying Costa , James Kai , Raghuveer S. Makala
IPC分类号： G11C11/00
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

6. 发明授权

US08551855B2 Memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same 有权
标题翻译：包括与转向元件兼容的碳基可逆电阻开关元件的存储单元及其形成方法
公开(公告)号：US08551855B2
公开(公告)日：2013-10-08
申请号：US12834942
申请日：2010-07-13
申请人： Huiwen Xu , Er-Xuan Ping , Xiying Costa
发明人： Huiwen Xu , Er-Xuan Ping , Xiying Costa
IPC分类号： H01L21/20
CPC分类号： H01L45/1675 , H01L21/02115 , H01L21/02274 , H01L21/3146 , H01L21/32139 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L45/1683
摘要： Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.
摘要翻译：提供了存储单元和形成这种存储单元的方法，其包括耦合到具有增加的电阻率的碳基可逆电阻率切换材料的转向元件和小于转向元件的最大电流能力的开关电流用于控制通过碳基可逆电阻率开关材料的电流。在具体实施例中，根据本发明的方法和装置形成具有第一宽度的转向元件，例如二极管，该第二宽度与第二宽度小于第一宽度的可逆电阻率开关材料（例如aC）耦合。

7. 发明申请

US20130163336A1 Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory 有权
标题翻译：通过控制选择栅极电压擦除操作，用于3D非易失性存储器
公开(公告)号：US20130163336A1
公开(公告)日：2013-06-27
申请号：US13332844
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa , Chenfeng Zhang
发明人： Haibo Li , Xiying Costa , Chenfeng Zhang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
摘要翻译：用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极（SGD）和源极选择栅极（SGS）。在一种方法中，驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压，同时将擦除电压施加到位线或源极线。可以产生在选择栅极处更一致的栅极引起的漏极漏极（GIDL），以对NAND串的体进行充电。此外，可以用擦除电压来升高选择栅极电压，以避免导致退化的选择栅极之间的过多的漏极 - 栅极电压。选择栅极电压的升高可以从擦除操作的第一次擦除验证迭代开始，或者以预定或自适应确定的擦除验证迭代（例如基于编程擦除周期的数量）开始。

8. 发明申请

US20120236624A1 Balanced Method for Programming Multi-Layer Cell Memories 有权
标题翻译：用于编程多层单元存储器的平衡方法
公开(公告)号：US20120236624A1
公开(公告)日：2012-09-20
申请号：US13051885
申请日：2011-03-18
申请人： Xiying Costa , Yibo Nian , Roy Scheuerlein , Tz-Yi Liu , Chandrasekhar Reddy Gorla
发明人： Xiying Costa , Yibo Nian , Roy Scheuerlein , Tz-Yi Liu , Chandrasekhar Reddy Gorla
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2013/0076 , G11C2013/0092 , G11C2213/32
摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.
摘要翻译：改进的多级金属氧化物存储单元的编程方法平衡施加的电压和电流，以提供更好的性能。通过为编程中要实现的目标电阻状态确定适当的编程电压和电流限制，然后施加具有确定的设定电气特性的脉冲来实现将存储器单元转换到较低电阻状态的设置编程。将存储器单元转换到较高电阻状态的复位编程通过确定编程中要实现的状态的适当编程电压和可选的电流限制，然后施加具有确定的电特性的脉冲来实现。用于确定适当的设置或复位编程电压和电流值的算法提供有效的编程，而不会对存储元件造成影响。编程脉冲的电气特性可以存储在表查找算法中使用的数据表中。

9. 发明授权

US08787094B2 Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits 有权
标题翻译：用于3D非易失性存储器的软擦除操作，选择性地禁止传递的位
公开(公告)号：US08787094B2
公开(公告)日：2014-07-22
申请号：US13450294
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C11/34 , G11C16/14 , G11C16/16 , G11C16/04
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障位。

10. 发明申请

US20130279256A1 Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits 有权
标题翻译：用于选择性禁止通过位的3D非易失性存储器的软擦除操作
公开(公告)号：US20130279256A1
公开(公告)日：2013-10-24
申请号：US13450294
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。

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