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51. 发明授权

US4688152A Molded pin grid array package GPT 失效
标题翻译：模压针阵列封装GPT
公开(公告)号：US4688152A
公开(公告)日：1987-08-18
申请号：US895395
申请日：1986-08-11
申请人： Chok J. Chia
发明人： Chok J. Chia
IPC分类号： H01L23/498 , H05K7/06
CPC分类号： H01L23/49827 , H01L2224/48091 , Y10T29/49146
摘要： A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins. The other flat-faced mold platen contains molding cavities that are in registry with and slightly larger than the PW boards. The mold cavities include a series of ribs that are distributed around the cavity periphery. These ribs bear against the PW board when the mold is assembled so that the PW board is centered and pressed against the flat face of first platen in the region outboard of the pin-grid pattern. When a liquified plastic encapsulant is forced into the mold the cavities will be filled and the liquid will be excluded from the pin side of the PW board.
摘要翻译：通过从具有电镀通孔的印刷电路板开始，可以容纳线引脚，从而创建一个针格栅封装。引脚被固定就位，从PW板的一个面向外延伸，形式为通常是多个同心环的所需结构的销栅格阵列形式，从而产生预定间隔的正方形网格图案。相对的PW板面包括固定半导体管芯的中心无引脚区域。 PW板的该面包括将每个引脚连接到围绕半导体管芯的阵列的多个布线迹线。迹线通过线接合或者使用带组件接合的蜘蛛组件连接到半导体管芯的接合焊盘。 PW板位于模具中，该模具具有平坦的第一压板，其包含将容纳封装销的切口区域。另一个平面模具压板包含与PW板对准并略大的模制腔。模腔包括分布在腔周边周围的一系列肋。当模具组装时，这些肋承载在PW板上，使得PW板在针脚格栅图案外侧的区域中心并压靠在第一压板的平面上。当液态塑料密封剂被迫进入模具时，空腔将被填充，并且液体将从PW板的销侧排除。

52. 发明授权

US07804167B2 Wire bond integrated circuit package for high speed I/O 有权
标题翻译： Wire Bond集成电路封装，适用于高速I / O
公开(公告)号：US07804167B2
公开(公告)日：2010-09-28
申请号：US11565701
申请日：2006-12-01
申请人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
发明人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/45147 , H01L2224/48233 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
摘要翻译：一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装基板和紧邻所述接地环形成的第一多个接合指，用于在所述封装基板和所述管芯之间附接第一组I / O信号接合线。

53. 发明申请

US20100067207A1 SEMICONDUCTOR PACKAGE AND METHOD USING ISOLATED VSS PLANE TO ACCOMMADATE HIGH SPEED CIRCUITRY GROUND ISOLATION 有权
标题翻译：半导体封装和使用隔离的VSS平面到接地高速电路分离的方法
公开(公告)号：US20100067207A1
公开(公告)日：2010-03-18
申请号：US12625457
申请日：2009-11-24
申请人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
发明人： Maurice O. Othieno , Chok J. Chia , Amar J. Amin
IPC分类号： H01R9/00 , H01L23/48
CPC分类号： H01L23/50 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/48091 , H01L2224/4943 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
摘要翻译：本发明的实施例包括半导体集成电路封装，其包括可以具有附接到其上的集成电路管芯的衬底。该封装包括与用于接地封装的低速电路的地平面电隔离的专用高速接地层。

54. 发明申请

US20080128919A1 WIRE BOND INTEGRATED CIRCUIT PACKAGE FOR HIGH SPEED I/O 有权
标题翻译：用于高速I / O的线束集成电路封装
公开(公告)号：US20080128919A1
公开(公告)日：2008-06-05
申请号：US11565701
申请日：2006-12-01
申请人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
发明人： Clifford Fishley , Abiola Awujoola , Leonard Mora , Amar Amin , Maurice Othieno , Chok J. Chia
IPC分类号： H01L23/49 , H01L21/44
CPC分类号： H01L23/66 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L2224/451 , H01L2224/45147 , H01L2224/48233 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00015 , H01L2224/05599
摘要： An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the die and the package substrate, and a first plurality of bond fingers formed immediately adjacent to the ground bonding ring for attaching a first set of I/O signal bond wires between the package substrate and the die.
摘要翻译：一种集成电路封装，包括封装基板，形成在封装基板上的管芯安装焊盘，用于将管芯固定到封装基板;形成在封装基板上的接地环，用于将芯和I / O接地线连接在管芯和管芯之间; 所述封装衬底以及紧邻所述接地环形成的第一多个接合指，用于在所述封装衬底和所述管芯之间附接第一组I / O信号接合线。

55. 发明授权

US06991147B2 Insulated bonding wire tool for microelectronic packaging 失效
标题翻译：用于微电子封装的绝缘接合线工具
公开(公告)号：US06991147B2
公开(公告)日：2006-01-31
申请号：US10642706
申请日：2003-08-18
申请人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Owai H. Low , Ramaswamy Ranganathan
IPC分类号： B23K31/02 , B05D5/12
CPC分类号： H01L24/85 , H01L23/4952 , H01L24/45 , H01L24/48 , H01L24/78 , H01L2224/05554 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/78301 , H01L2224/8502 , H01L2224/85181 , H01L2224/8592 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01079 , H01L2924/20753 , H01L2924/06 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.
摘要翻译：一种用于绝缘接合线的方法，包括以下步骤：将接合线附接到接合焊盘，并且用绝缘液体涂覆接合线，同时将接合线通过接合工具从接合焊盘牵引到封装引线。

56. 发明授权

US06285077B1 Multiple layer tape ball grid array package 有权
标题翻译：多层磁带球栅阵列封装
公开(公告)号：US06285077B1
公开(公告)日：2001-09-04
申请号：US09377887
申请日：1999-08-19
申请人： Chok J. Chia , Seng-Sooi Allen Lim , Qwai Hoong Low
发明人： Chok J. Chia , Seng-Sooi Allen Lim , Qwai Hoong Low
IPC分类号： H01L2348
CPC分类号： H01L23/3128 , H01L23/49833 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.
摘要翻译：公开了一种用于集成电路的封装。该包装包括柔性带的两层（顶层和底层），每层具有顶表面和底表面，顶表面具有金属迹线。模具安装在两层的顶部，引线接合将模具上的接合焊盘连接到两个柔性带中的每一个上的金属迹线。金属迹线沿着柔性带的顶表面布线，并通过带中的孔耦合到焊球。这些焊球沿着封装的底部安装并用作印刷电路板的电接口。底层带中的另外的孔允许焊球延伸穿过底层带，使得它们可以电耦合到顶层带上的迹线。

57. 发明授权

US06861343B2 Buffer metal layer 失效
标题翻译：缓冲金属层
公开(公告)号：US06861343B2
公开(公告)日：2005-03-01
申请号：US10267410
申请日：2002-10-09
申请人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
发明人： Chok J. Chia , Qwai H. Low , Ramaswamy Ranganathan
IPC分类号： H01L23/367 , H01L23/373 , H01L23/522 , H01L23/552 , H01L21/44
CPC分类号： H01L23/552 , H01L23/367 , H01L23/3735 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit having a top passivation layer and bonding pads, where the improvement is a metal layer overlying all of the integrated circuit. The metal layer overlies the top passivation layer and is not in electrical contact with any of the bonding pads. In this manner, there is a structure that is added to the integrated circuit which has a relatively high thermal conductivity, and which also has a relatively high structural strength. With these two added properties, the occurrence of stress cracks, such as those induced by plastic molded packages, is reduced, and hot spots tend to be dissipated. Thus, the overlying metal layer tends to improve the reliability of the integrated circuit.
摘要翻译：具有顶部钝化层和接合焊盘的集成电路，其中改进是覆盖所有集成电路的金属层。金属层覆盖在顶部钝化层上，并且不与任何焊盘焊接。以这种方式，具有添加到具有相对较高导热性并且还具有相对较高的结构强度的集成电路的结构。通过这两个添加的性质，减少了由塑料模制包装引起的应力裂纹的发生，并且热点趋于消散。因此，上覆金属层倾向于提高集成电路的可靠性。

58. 发明授权

US06429534B1 Interposer tape for semiconductor package 有权
标题翻译：用于半导体封装的插入式磁带
公开(公告)号：US06429534B1
公开(公告)日：2002-08-06
申请号：US09478972
申请日：2000-01-06
申请人： Qwai H. Low , Chok J. Chia , Maniam Alagaratnam
发明人： Qwai H. Low , Chok J. Chia , Maniam Alagaratnam
IPC分类号： H01L2348
CPC分类号： H01L23/49827 , H01L23/49833 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/4911 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/14 , H01L2924/15173 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.
摘要翻译：提供了一种提供管芯和封装衬底之间的电连通的插入器带。插入器带的尺寸可以变化以适应相同封装基板的各种管芯尺寸。插入器带包括一列迹线。在迹线阵列和模具之间形成第一组引线键合。在迹线阵列和封装衬底之间形成第二组线接合。

59. 发明授权

US06425179B1 Method for assembling tape ball grid arrays 有权
标题翻译：胶带球栅阵列组装方法
公开(公告)号：US06425179B1
公开(公告)日：2002-07-30
申请号：US09417255
申请日：1999-10-12
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H01L21/60 , H01L23/00 , H05K3/34
CPC分类号： H01L24/86 , H01L23/562 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , Y10T29/49144 , Y10T29/49146 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： According to the present invention, a method for creating a package for a semiconductor die, the package comprising a flexible tape, comprises the following steps. A support with an opening has a plurality of arms extending through at a portion of the opening. For example, for a square opening, there may be eight arms, two extending from each side of the opening. The arms preferably form a “z” shape or some other shape with a transverse component. The flexible tape is then attached to the ends of the arms within the opening such that the flexible tape is supported by the arms. A die is attached to the flexible tape, the die is preferably covered with a molding compound, and the die/flexible tape assembly is scribed from the support, thereby creating an individual package.
摘要翻译：根据本发明，一种用于制造用于半导体管芯的封装的方法，包括柔性带的封装包括以下步骤。具有开口的支撑件具有在开口的一部分延伸穿过的多个臂。例如，对于方形开口，可以有八个臂，两个从开口的每一侧延伸。臂优选地形成具有横向分量的“z”形或一些其它形状。然后将柔性带附接到开口内的臂的端部，使得柔性带由臂支撑。将模具附接到柔性带上，模具优选用模制化合物覆盖，并且模具/柔性带组件从支撑件划刻，从而形成单独的包装。

60. 发明授权

US6057594A High power dissipating tape ball grid array package 失效
标题翻译：大功率消磁带球栅阵列封装
公开(公告)号：US6057594A
公开(公告)日：2000-05-02
申请号：US842379
申请日：1997-04-23
申请人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
发明人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
IPC分类号： H01L23/433 , H01L23/495 , H01L23/498 , H01L23/34 , H01L23/48
CPC分类号： H01L23/4334 , H01L23/49572 , H01L23/49816 , H01L2924/0002
摘要： A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.
摘要翻译：模制的带状球栅阵列封装具有基底结构，其包括导热基底和柔性带，该柔性带从柔性带和基底之间的模制塑料材料的表面上的相对区域延伸。柔性带具有至少一个导电金属引线图案，其可以被定位在面向基板的带的一侧，并具有多个孔，用于将导电引线图案从带的相对侧暴露以进行焊球接合。半导体集成电路芯片通过引线将芯片上的接合焊盘互连到金属引线图案，在柔性带的相对区域之间的基板的中心部分上安装。然后将芯片和引线接合封装在基板上。该结构是经济的并且允许来自集成电路的高功率耗散。在制造集成电路封装中的成型工艺是经济的，并且易于使用注塑成型。

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