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51. 发明授权

US07022561B2 CMOS device 有权
标题翻译： CMOS器件
公开(公告)号：US07022561B2
公开(公告)日：2006-04-04
申请号：US10307619
申请日：2002-12-02
申请人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
发明人： Chien-Chao Huang , Chao-Hsing Wang , Chung-Hu Ge , Chenming Hu
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828
摘要： A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.
摘要翻译：一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸在NMOS器件上的应力层。

52. 发明申请

US20050133817A1 Improved Cobalt Silicidation Process for Substrates with a Silicon Germanium Layer 有权
标题翻译：具有硅锗层的衬底的改进的钴硅化工艺
公开(公告)号：US20050133817A1
公开(公告)日：2005-06-23
申请号：US10710012
申请日：2004-06-11
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21/285 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/76
CPC分类号： H01L29/66636 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/1054 , H01L29/665 , H01L29/66545 , Y10S438/933
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
摘要翻译：一种方法包括在半导体衬底上提供半导体合金层，在半导体合金层上形成栅极结构，在半导体衬底的栅极结构的两侧形成源区和漏极区，去除半导体合金层的至少一部分覆盖源极和漏极区域，并且在源极和漏极区域上形成金属硅化物区域。

53. 发明授权

US06900502B2 Strained channel on insulator device 有权
标题翻译：应变绝缘体上的通道
公开(公告)号：US06900502B2
公开(公告)日：2005-05-31
申请号：US10407761
申请日：2003-04-03
申请人： Chung-Hu Ge , Chao-Hsuing Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
发明人： Chung-Hu Ge , Chao-Hsuing Wang , Chien-Chao Huang , Wen-Chin Lee , Chenming Hu
IPC分类号： H01L21/00 , H01L21/30 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/02 , H01L29/72 , H01L29/772
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/84 , H01L27/1203 , H01L29/7848
摘要： A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.
摘要翻译：半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

54. 发明授权

US06878610B1 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US06878610B1
公开(公告)日：2005-04-12
申请号：US10228545
申请日：2002-08-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/36 , H01L21/84 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.
摘要翻译：已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理允许为SiGe层实现优化的弛豫和缺陷密度。在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的，低缺陷密度SiGe层。

55. 发明授权

US6051345A Method of producing phase shifting mask 失效
标题翻译：生产相移掩模的方法
公开(公告)号：US6051345A
公开(公告)日：2000-04-18
申请号：US95406
申请日：1998-06-10
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： G03F1/26 , G03F1/29 , G03F1/30 , G03F1/72 , G06F9/00
CPC分类号： G03F1/29 , G03F1/26 , G03F1/30 , G03F1/72
摘要： A method for producing a phase shifting mask comprising the steps of first forming a phase shifting layer capable of shifting incoming light by a 360.degree. phase shift angle over a transparent substrate, or forming two phase shifting layers, which are each capable of shifting incoming light by a 180.degree. phase shift angle, before carrying out the steps required to fabricate the phase shifting mask in a conventional method. With the additional phase shifting layer or layers, damage to the transparent substrate due to etching is prevented. Moreover, phase errors caused by defective regions in the phase shifting mask can be removed, easily resulting in the formation of a defect-free mask.
摘要翻译：一种相移掩模的制造方法，包括以下步骤：首先形成能够将入射光以360°相移角移动到透明基板上的相移层，或者形成两个移相层，每个移相层能够移入入射光在进行以常规方法制造相移掩模所需的步骤之前，通过180°相移角。通过附加的相移层或层，可以防止由蚀刻引起的对透明基板的损伤。此外，可以去除由相移掩模中的缺陷区域引起的相位误差，容易导致形成无缺陷掩模。

56. 发明授权

US5965303A Method of fabricating a phase shift mask utilizing a defect repair machine 失效
标题翻译：使用缺陷修复机制造相移掩模的方法
公开(公告)号：US5965303A
公开(公告)日：1999-10-12
申请号：US30810
申请日：1998-02-26
申请人： Chien-Chao Huang
发明人： Chien-Chao Huang
IPC分类号： G03F1/00 , G03F1/26 , G03F1/32 , G03F9/00
CPC分类号： G03F9/70 , G03F1/26
摘要： A method of fabricating a single layer phase shift mask is provided. The method is characterized by depositing an opaque layer by using a defect repair machine on a given place of the phase shift layer formed by a conventional method. The opaque layer is formed on the alignment mark. The single layer phase shift mask of the invention can provide better resolution for transferred patterns projected on the wafer and can avoid registration deviation and reduce a problem of misalignment of the alignment mark efficiently by decreasing the transmittance of the alignment mark, such as a reticule mark or a stepper mark.
摘要翻译：提供一种制造单层相移掩模的方法。该方法的特征在于通过使用在常规方法形成的相移层的给定位置上的缺陷修复机来沉积不透明层。在对准标记上形成不透明层。本发明的单层相移掩模可以为投影在晶片上的转印图案提供更好的分辨率，并且可以避免对准偏差，并通过降低对准标记的透光率（如网状标记）有效地减少对准标记的未对准的问题或步进标记。

57. 发明授权

US08564018B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US08564018B2
公开(公告)日：2013-10-22
申请号：US12038091
申请日：2008-02-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： H01L21/02
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.
摘要翻译：公开了一种用于集成电路的结构。该结构包括晶体衬底和四个结晶层。第一晶格常数的第一晶体层位于晶体衬底上。第二晶体层具有不同于第一晶格常数的第二晶格常数，并且位于所述第一晶体层上。第三晶体层具有与所述第二晶格常数不同的第三晶格常数，并且位于所述第二晶体层上。应变的第四晶体层至少部分地包括MOSFET器件。

58. 发明申请

US20120211675A1 MASK MAKING DECISION FOR MANUFACTURING (DFM) ON MASK QUALITY CONTROL 有权
标题翻译：制造（DFM）掩蔽质量控制制作决定
公开(公告)号：US20120211675A1
公开(公告)日：2012-08-23
申请号：US13398165
申请日：2012-02-16
申请人： Chih-Chiang Tu , Chien-Chao Huang
发明人： Chih-Chiang Tu , Chien-Chao Huang
IPC分类号： G01N21/956 , G21K5/00
CPC分类号： G03F1/84
摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.
摘要翻译：本公开提供了一种制造掩模的方法。该方法包括将多个模式特征分配给不同的数据类型; 在掩模上写入多个图案特征; 根据分配的数据类型检查具有不同检查灵敏度的多个图案特征; 以及根据所述多个图案特征的检查来修复所述掩模上的所述多个图案特征。

59. 发明授权

US07638376B2 Method for forming SOI device 有权
标题翻译： SOI器件形成方法
公开(公告)号：US07638376B2
公开(公告)日：2009-12-29
申请号：US11652624
申请日：2007-01-12
申请人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
发明人： Cheng-Kuo Wen , Chien-Chao Huang , Hao-Yu Chen , Fu-Liang Yang , Hsun-Chih Tsao
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/78603 , H01L21/743 , H01L21/76283 , H01L21/84 , H01L29/66772 , H01L29/785
摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.
摘要翻译：提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

60. 发明授权

US07452805B2 Aluminum based conductor for via fill and interconnect 有权
标题翻译：用于通孔填充和互连的铝基导体
公开(公告)号：US07452805B2
公开(公告)日：2008-11-18
申请号：US11385923
申请日：2006-03-20
申请人： Chao-Hsiung Wang , Chien-Chao Huang , Chenming Hu , Horng-Huei Tseng
发明人： Chao-Hsiung Wang , Chien-Chao Huang , Chenming Hu , Horng-Huei Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/2855 , H01L21/76838 , H01L21/76849 , H01L21/76877
摘要： A semiconductor device including a dielectric layer having a opening form therein having a cross-sectional area of less than 1 μm2 and a PVD aluminum base conductor filled in the opening.
摘要翻译：一种半导体器件，包括其中具有小于1μm2的横截面积的开口形式的电介质层和填充在该开口中的PVD铝基底导体。

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