专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明申请

US20080125984A1 Spatially Assisted Fault Reporting Method, System and Apparatus 审中-公开
标题翻译：空间辅助故障报告方法，系统和设备
公开(公告)号：US20080125984A1
公开(公告)日：2008-05-29
申请号：US11534898
申请日：2006-09-25
申请人： Veselin Skendzic , Daniel N. Morman , George C. Blat , Ping Jiang
发明人： Veselin Skendzic , Daniel N. Morman , George C. Blat , Ping Jiang
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G05B23/0267
摘要： Methods and systems for spatially assisted fault reporting in a distribution system. Typical steps of the methods may include determining the location of the fault or the distance to the fault, generating and storing a plurality of waypoints representative of the route of the distribution system, processing the plurality of waypoints, determining spatial coordinates of the fault, generating a fault report, and communicating the fault report. The waypoints may be contained within an XML file which is compressed with a compression algorithm prior to sending and which is decompressed prior to use at a receiving end to create a visual template or overlay for displaying the fault information
摘要翻译：配电系统中空间辅助故障报告的方法和系统。方法的典型步骤可以包括确定故障的位置或与故障的距离，生成和存储表示分配系统的路线的多个航路点，处理多个航路点，确定故障的空间坐标，产生故障报告，并通报故障报告。路标点可以包含在XML文件中，该文件在发送之前用压缩算法压缩，并且在接收端使用之前进行解压缩以创建用于显示故障信息的可视模板或覆盖

52. 发明申请

US20080057701A1 METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION 审中-公开
标题翻译：用于防止集成电路制造过程中的耐药性的方法
公开(公告)号：US20080057701A1
公开(公告)日：2008-03-06
申请号：US11469598
申请日：2006-09-01
申请人： Edward Raymond Engbrecht , William W. Dostalik , Ping Jiang , Edmund Burke , Laura M. Matz
发明人： Edward Raymond Engbrecht , William W. Dostalik , Ping Jiang , Edmund Burke , Laura M. Matz
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/0276 , H01L21/0332 , H01L21/31144
摘要： A method of manufacturing an integrated circuit comprising fabricating a dual damascene interconnect. Fabricating the interconnect including forming a via opening in a surface of an inter-layer dielectric (ILD) located over a semiconductor substrate. Fabricating the interconnect also includes depositing a sacrificial fill material over the surface and in the via opening. Fabricating the interconnect further includes removing the sacrificial fill material from the surface, depositing a poison-blocking-layer over the surface and forming a trench pattern in a photoresist layer formed over the poison-blocking-layer. The poison-blocking-layer is configured to prevent poisons from entering the photoresist layer.
摘要翻译：一种制造集成电路的方法，包括制造双镶嵌互连。制造互连，包括在位于半导体衬底上的层间电介质（ILD）的表面中形成通孔。制造互连件还包括在表面上和通孔开口中沉积牺牲填充材料。制造互连还包括从表面去除牺牲填充材料，在表面上沉积毒物阻挡层并在形成在毒物阻挡层上的光致抗蚀剂层中形成沟槽图案。毒物阻断层被配置为防止毒物进入光致抗蚀剂层。

53. 发明授权

US07338888B2 Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same 有权
标题翻译：用于制造具有硅化物栅电极的半导体器件的方法和包括其的集成电路的制造方法
公开(公告)号：US07338888B2
公开(公告)日：2008-03-04
申请号：US10810759
申请日：2004-03-26
申请人： Jiong-Ping Lu , Haowen Bu , Shaofeng Yu , Ping Jiang
发明人： Jiong-Ping Lu , Haowen Bu , Shaofeng Yu , Ping Jiang
IPC分类号： H01L21/28 , H01L21/44 , H01L21/76 , H01L21/4763
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。除了其他可能的步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成多晶硅栅电极，并在靠近多晶硅栅电极的衬底（110）中形成源/漏区（170）。该方法还包括在源极/漏极区域（170）上形成阻挡层（180），阻挡层（180）包括金属硅化物，并硅化多晶硅栅电极以形成硅化物栅电极（150）。

54. 发明申请

US20070275561A1 GAS SWITCHING DURING AN ETCH PROCESS TO MODULATE THE CHARACTERISTICS OF THE ETCH 有权
标题翻译：在ETCH过程中的气体开关调节ETCH的特性
公开(公告)号：US20070275561A1
公开(公告)日：2007-11-29
申请号：US11420405
申请日：2006-05-25
申请人： Ping Jiang , Francis Celii
发明人： Ping Jiang , Francis Celii
IPC分类号： H01L21/311 , H01L21/302
CPC分类号： H01L21/31144 , H01L21/30655 , H01L21/31116 , H01L21/31138 , H01L21/76808
摘要： Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.
摘要翻译：在蚀刻过程中使用气体切换来调制蚀刻的特性。蚀刻过程包括至少三个步骤的序列，其中该序列重复至少一次。例如，第一步可能导致氧化物（108）的高蚀刻速率，而第二步骤是聚合物涂覆步骤，第三步骤导致氧化物的低蚀刻速率和另一种材料（114）的高蚀刻速率， /或溅射。

55. 发明申请

US20070067625A1 System and method for enabling secure access to a program of a headless server device 有权
标题翻译：用于实现对无头服务器设备的程序的安全访问的系统和方法
公开(公告)号：US20070067625A1
公开(公告)日：2007-03-22
申请号：US11214391
申请日：2005-08-29
申请人： Ping Jiang , Kevin Carson
发明人： Ping Jiang , Kevin Carson
IPC分类号： H04L9/00
CPC分类号： H04L63/10 , H04L63/083
摘要： Provided is a system and method for enabling secure access to a desired end-point server program of at least one end-point server program. The system includes a server having a security server program and the end-point server programs, and a client. During operation, the server establishes a first connection with the client via a known port, causes an end-point program applet and web page associated with the desired end-point server program to be forwarded to the client. While executing the security server program, the server: verifies client access rights via a first encryption means, generates, encrypts and transmits to the client a random port number and a session key, and detects establishment of a second connection between the client and a random port of the server. The second connection enables secure access by the client to the desired end-point server program using a second encryption means and the session key.
摘要翻译：提供了一种用于实现对至少一个端点服务器程序的期望终点服务器程序的安全访问的系统和方法。该系统包括具有安全服务器程序和端点服务器程序的服务器以及客户机。在操作期间，服务器通过已知端口建立与客户端的第一连接，导致与期望的端点服务器程序相关联的端点程序小程序和网页被转发到客户端。在执行安全服务器程序时，服务器：通过第一加密手段验证客户端的访问权限，生成加密并向客户端发送随机端口号和会话密钥，并且检测客户机与随机的第二连接的建立端口的服务器。第二连接使得能够使用第二加密装置和会话密钥使客户端对期望的端点服务器程序的安全访问。

56. 发明授权

US07148143B2 Semiconductor device having a fully silicided gate electrode and method of manufacture therefor 有权
标题翻译：具有全硅化物栅电极的半导体器件及其制造方法
公开(公告)号：US07148143B2
公开(公告)日：2006-12-12
申请号：US10808168
申请日：2004-03-24
申请人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
发明人： Haowen Bu , Jiong-Ping Lu , Shaofeng Yu , Ping Jiang , Clint Montgomery
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/461 , H01L21/302
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
摘要翻译：本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。除了其它可能的元件之外，半导体器件（100）包括位于衬底（110）上方的硅化栅电极（150），硅化栅电极（150）具有位于其侧壁上的栅极侧壁间隔物（160）。半导体器件（100）还包括位于靠近硅化物栅电极（150）的衬底（110）中的源/漏区（170）和位于源/漏区（170）中的硅化源/漏区（180）并且至少部分地在栅极侧壁间隔件（160）下方。

57. 发明申请

US20050255687A1 Plasma treatment for silicon-based dielectrics 有权
标题翻译：硅基电介质的等离子体处理
公开(公告)号：US20050255687A1
公开(公告)日：2005-11-17
申请号：US10843957
申请日：2004-05-11
申请人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
发明人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02123 , H01L21/0234 , H01L21/3105 , H01L21/316 , H01L21/76807 , H01L21/76808
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).
摘要翻译：本发明的一个实施例是制造半导体晶片的方法。该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤（步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

58. 发明申请

US20050130845A1 Method and composition for the triggered release of polymer-degrading agents for oil field use 审中-公开
标题翻译：用于油田使用的聚合物降解剂的触发释放的方法和组合物
公开(公告)号：US20050130845A1
公开(公告)日：2005-06-16
申请号：US10990213
申请日：2004-11-16
申请人： Michael Freeman , Monica Norman , David Ballard , Ping Jiang , Kenneth Symes , Kishor Mistry
发明人： Michael Freeman , Monica Norman , David Ballard , Ping Jiang , Kenneth Symes , Kishor Mistry
IPC分类号： C09K8/536 , C09K8/66 , C09K8/68 , C09K8/92 , E21B43/00
CPC分类号： C09K8/92 , C09K8/536 , C09K8/665 , C09K8/68 , Y10S507/902 , Y10S507/921 , Y10S507/922
摘要： Disclosed are methods and related compositions for altering the physical and chemical properties of a substrate used in hydrocarbon exploitation, such as in downhole drilling operations. In a preferred embodiment a method involves formulating a fluid, tailored to the specific drilling conditions, that contains one or more inactivated enzymes. Preferably the enzyme is inactivated by encapsulation in a pH responsive material. After the fluid has been introduced into the well bore, one or more triggering signals, such as a change in pH, is applied to the fluid that will activate or reactivate the inactivated enzyme, preferably by causing it to be released by the encapsulation material. The reactivated enzyme is capable of selectively acting upon a substrate located downhole to bring about the desired change in the chemical or physical properties of the substrate.
摘要翻译：公开了用于改变用于烃开采中的底物的物理和化学性质的方法和相关组合物，例如在井下钻井操作中。在优选实施方案中，一种方法包括配制包含一种或多种灭活酶的特定钻井条件的流体。优选地，酶通过包封在pH响应材料中而失活。在将流体引入井眼之后，将一种或多种触发信号（诸如pH变化）施加到将激活或重新活化失活的酶的流体，优选通过使其被包封材料释放。再活化的酶能够选择性地作用在位于井下的基质上，从而引起基底的化学或物理性质的所需变化。

59. 发明授权

US06900123B2 BARC etch comprising a selective etch chemistry and a high polymerizing gas for CD control 有权
标题翻译： BARC蚀刻包括选择性蚀刻化学和用于CD控制的高聚合气体
公开(公告)号：US06900123B2
公开(公告)日：2005-05-31
申请号：US10393317
申请日：2003-03-20
申请人： Ping Jiang , Robert Kraft , Mark Somervell
发明人： Ping Jiang , Robert Kraft , Mark Somervell
IPC分类号： H01L21/3065 , H01L21/027 , H01L21/033 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： A BARC etch comprises a selective etch chemistry in combination with a high-polymerizing gas for CD control. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a thick BARC layer (120) is deposited to fill the via (116) and coat the IMD (110). A trench resist pattern (125) is formed over the BARC layer (120). Then, the exposed portion of BARC (120) over the IMD (110) is etched using a high-polymerizing gas added to a selective etch chemistry. The more polymerizing gas passivates the trench resist (125) sidewall to preserve or improve the trench CD. During the main trench etch, portions of BARC (120) remain in the via to protect the etch-stop (104) at the bottom of the via (116).
摘要翻译： BARC蚀刻包括与用于CD控制的高聚合气体组合的选择性蚀刻化学。 BARC蚀刻可以以通孔 - 第一双镶嵌方法使用。在经过（116）图案和蚀刻之后，沉积厚的BARC层（120）以填充通孔（116）并涂覆IMD（110）。在BARC层（120）之上形成沟槽抗蚀剂图案（125）。然后，使用添加到选择性蚀刻化学品的高聚合气体来蚀刻在IMD（110）上的BARC（120）的暴露部分。更多的聚合气体钝化沟槽抗蚀剂（125）侧壁以保留或改善沟槽CD。在主沟槽蚀刻期间，BARC（120）的部分保留在通孔中，以保护通孔（116）底部的蚀刻停止（104）。

60. 发明授权

US06642518B1 Assembly and method for improved scanning electron microscope analysis of semiconductor devices 有权
标题翻译：用于改进半导体器件扫描电子显微镜分析的装配和方法
公开(公告)号：US06642518B1
公开(公告)日：2003-11-04
申请号：US10176873
申请日：2002-06-21
申请人： Fred Y. Clark , James D. Krouse , Ping Jiang , Robyn R. Carlson
发明人： Fred Y. Clark , James D. Krouse , Ping Jiang , Robyn R. Carlson
IPC分类号： H01J3710
CPC分类号： G01N23/225 , H01J2237/004 , H01J2237/2809 , H01J2237/2814
摘要： An assembly and method for improved scanning electron microscope analysis of semiconductor devices include a structure including a first layer and a second layer, the second layer shrinking substantially when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV, and at least part of the surface of the structure coated with a material composed of Iridium, wherein the coating is of sufficient thickness to reduce shrinkage of the second layer to approximately a predetermined amount when the structure is examined with a scanning electron microscope having a beam energy of at least 1.5 KeV.
摘要翻译：用于改进半导体器件的扫描电子显微镜分析的组件和方法包括包括第一层和第二层的结构，当使用具有至少1.5KeV的束能的扫描电子显微镜检查结构时，第二层基本上收缩，并且涂覆有由铱构成的材料的结构的表面的至少一部分，其中当使用具有光束的扫描电子显微镜检查结构时，涂层具有足够的厚度以减小第二层的收缩至约预定量至少1.5 KeV的能量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式