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51. 发明申请

US20080246152A1 SEMICONDUCTOR DEVICE WITH BONDING PAD 审中-公开
标题翻译：具有粘接垫的半导体器件
公开(公告)号：US20080246152A1
公开(公告)日：2008-10-09
申请号：US11696296
申请日：2007-04-04
申请人： Ming-Chyi Liu , Yuan-Hung Liu , Gwo-Yuh Shiau , Yuan-Chih Hsieh , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Ming-Chyi Liu , Yuan-Hung Liu , Gwo-Yuh Shiau , Yuan-Chih Hsieh , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L27/14636 , H01L27/14643 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45166 , H01L2224/4807 , H01L2224/4845 , H01L2224/48463 , H01L2224/48505 , H01L2224/48624 , H01L2224/48824 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/00014 , H01L2224/05666 , H01L2224/45124 , H01L2224/05655 , H01L2924/00
摘要： A semiconductor device with a bonding pad is provided. The semiconductor device includes a first substrate having a device area and a bonding area, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are disposed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is disposed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is disposed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad, and the first substrate is exposed through an opening in the lowermost metal pattern.
摘要翻译：提供具有接合焊盘的半导体器件。半导体器件包括具有器件面积和接合面积的第一衬底，其中第一衬底具有上表面和底表面。半导体元件设置在器件区域中的第一衬底的上表面上。在接合区域中的第一金属间介电层设置在基板的上表面上。最下面的金属图案设置在第一金属间介质层中，其中最下面的金属图形用作接合焊盘，第一基板通过最下面的金属图案中的开口露出。

52. 发明授权

US07385244B2 Flash memory devices with box shaped polygate structures 有权
标题翻译：具有盒形多孔结构的闪存设备
公开(公告)号：US07385244B2
公开(公告)日：2008-06-10
申请号：US11051845
申请日：2005-02-03
申请人： Yi-Shing Chang , Yeur-Luen Tu , Chia-Shiung Tsai , Wen-Ting Chu
发明人： Yi-Shing Chang , Yeur-Luen Tu , Chia-Shiung Tsai , Wen-Ting Chu
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.
摘要翻译：一种在多晶硅蚀刻工艺中形成改进的蚀刻硬掩模氧化物层的方法，包括提供包括相邻的第一裸露多晶硅部分和暴露的氧化物部分的平坦化的半导体晶片工艺表面; 选择性地蚀刻暴露的氧化物部分的厚度部分; 在暴露的多晶硅部分上热生长氧化物硬掩模层以形成氧化物硬掩模部分; 暴露出与至少一个氧化物硬掩模部分相邻的第二暴露的多晶硅部分; 并且蚀刻穿过第二暴露的多晶硅部分的厚度部分。

53. 发明授权

US07202130B2 Spacer for a split gate flash memory cell and a memory cell employing the same 有权
标题翻译：分离栅闪存单元的间隔器和采用其的存储单元
公开(公告)号：US07202130B2
公开(公告)日：2007-04-10
申请号：US10775290
申请日：2004-02-10
申请人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Yuan-Hung Liu , Chih-Ta Wu , Yeur-Luen Tu , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.
摘要翻译：间隔物，分裂栅极闪存单元及其相关方法。在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

54. 发明申请

US20070069328A1 SPLIT GATE FLASH DEVICES 审中-公开
标题翻译：分闸门闪存器件
公开(公告)号：US20070069328A1
公开(公告)日：2007-03-29
申请号：US11555712
申请日：2006-11-02
申请人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521
摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.
摘要翻译：提供了一种用于形成分离栅极闪光装置的方法。在一个实施例中，提供了其上形成介电层的半导体衬底。形成覆盖在电介质层上的导体层。掩蔽层沉积在导体层上。形成覆盖掩模层的光敏层。对感光层进行图案化和蚀刻以在其中形成开口图案。掩模层和导体层根据光敏层中的开口图案进行蚀刻。在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。隔离层填充在多个沟槽和掩蔽层上。掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

55. 发明授权

US07161204B2 DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area 有权
标题翻译： DRAM电容器结构具有增加的电极支持，用于防止工艺损坏和暴露的电极表面，以增加电容器面积
公开(公告)号：US07161204B2
公开(公告)日：2007-01-09
申请号：US11098112
申请日：2005-04-04
申请人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
发明人： Chun-Chieh Lin , Lan-Lin Chao , Chia-Shiung Tsai , Fu-Liang Yang , Chia-Hui Lin , Chanming Hu
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/0207 , H01L27/10817 , H01L28/91
摘要： A method for fabricating a high-density array of crown capacitors with increased capacitance while reducing process damage to the bottom electrodes is achieved. The process is particularly useful for crown capacitors for future DRAM circuits with minimum feature sizes of 0.18 micrometer or less. A conformal conducting layer is deposited over trenches in an interlevel dielectric (ILD) layer, and is polished back to form capacitor bottom electrodes. A novel photoresist mask and etching are then used to pattern the ILD layer to provide a protective interlevel dielectric structure between capacitors. The protective structures prevent damage to the bottom electrodes during subsequent processing. The etching also exposes portions of the outer surface of bottom electrodes for increased capacitance (>50%). In a first embodiment the ILD structure is formed between pairs of adjacent bottom electrodes, and in a second embodiment the ILD structure is formed between four adjacent bottom electrodes.
摘要翻译：实现了一种用于制造具有增加的电容的高密度阵列的冠状电容器的方法，同时减少了对底部电极的工艺损伤。该过程对于具有最小特征尺寸为0.18微米或更小的未来DRAM电路的冠电容器特别有用。在层间电介质（ILD）层中的沟槽上沉积共形导电层，并将其抛光回形成电容器底部电极。然后使用新颖的光致抗蚀剂掩模和蚀刻来对ILD层进行图案化，以在电容器之间提供保护层间电介质结构。保护结构可防止在后续处理期间损坏底部电极。蚀刻还暴露了底部电极的外表面的部分以增加电容（> 50％）。在第一实施例中，ILD结构形成在成对的相邻底部电极之间，并且在第二实施例中，ILD结构形成在四个相邻的底部电极之间。

56. 发明申请

US20060275984A1 METHOD FOR PREVENTING TRENCHING IN FABRICATING SPLIT GATE FLASH DEVICES 有权
标题翻译：用于防止在制造分离栅格闪存器件中进行TRENCHING的方法
公开(公告)号：US20060275984A1
公开(公告)日：2006-12-07
申请号：US11141902
申请日：2005-06-01
申请人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521
摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.
摘要翻译：提供了一种用于形成分离栅极闪光装置的方法。在一个实施例中，提供了其上形成介电层的半导体衬底。形成覆盖在电介质层上的导体层。掩蔽层沉积在导体层上。形成覆盖掩模层的光敏层。对感光层进行图案化和蚀刻以在其中形成开口图案。掩模层和导体层根据光敏层中的开口图案进行蚀刻。在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。隔离层填充在多个沟槽和掩蔽层上。掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

57. 发明申请

US20060170029A1 Novel process for erase improvement in a non-volatile memory device 有权
标题翻译：用于擦除非易失性存储器件中的擦除的新方法
公开(公告)号：US20060170029A1
公开(公告)日：2006-08-03
申请号：US11045850
申请日：2005-01-28
申请人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Shih-Chi Fu , Chia-Ta Hsieh , Wen-Ting Chu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115
摘要： A method of making embedded non-volatile memory devices includes forming a first mask layer overlying a polycrystalline silicon layer in a cell region and a peripheral region on a semiconductor substrate wherein the first mask layer has a plurality of openings in the cell region. Portions of the polycrystalline silicon layer exposed in the plurality of openings can be oxidized to form a plurality of poly-oxide regions, and the first mask layer can then be removed. The polycrystalline silicon layer not covered by the plurality of poly-oxide regions can be etched to form a plurality of floating gates, wherein etching the polycrystalline silicon layer is accompanied by a sputtering. A dielectric layer can then be formed, as well as a second mask layer in both the cell region and the peripheral region. The second mask layer in the cell region is partially etched back after a photoresist layer is formed over the second mask layer in the peripheral region. The dielectric layer is partially etched to form multiple thicknesses of the dielectric layer. The second mask layer is removed and a plurality of control gates are formed partially overlying the plurality of floating gates in the cell region.
摘要翻译：一种制造嵌入式非易失性存储器件的方法包括形成覆盖单元区域中的多晶硅层的第一掩模层和半导体衬底上的外围区域，其中第一掩模层在单元区域中具有多个开口。在多个开口中暴露的多晶硅层的一部分可以被氧化以形成多个多晶氧化物区域，然后可以去除第一掩模层。可以蚀刻不被多个多晶氧化物区域覆盖的多晶硅层以形成多个浮栅，其中蚀刻多晶硅层伴随着溅射。然后可以形成电介质层，以及在电池区域和周边区域中形成第二掩模层。在周边区域中的第二掩模层上形成光致抗蚀剂层之后，单元区域中的第二掩模层被部分地回蚀。电介质层被部分蚀刻以形成介电层的多个厚度。去除第二掩模层，并且多个控制栅极部分地覆盖在单元区域中的多个浮动栅极上。

58. 发明申请

US20050215004A1 Method of forming MIM capacitor electrodes 有权
标题翻译：形成MIM电容器电极的方法
公开(公告)号：US20050215004A1
公开(公告)日：2005-09-29
申请号：US10811657
申请日：2004-03-29
申请人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
发明人： Chih-Ta Wu , Kuo-Yin Lin , Tsung-Hsun Huang , Chung-Yi Yu , Lan-Lin Chao , Yeur-Luen Tu , Hsing-Lien Lin , Chia-Shiung Tsai
IPC分类号： H01G4/005 , H01L21/02 , H01L21/28 , H01L21/3205 , H01L21/44 , H01L23/522 , H01L29/06
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.
摘要翻译：公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能，在MIM电容器的制造中。该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

59. 发明授权

US06881622B2 Aqueous ammonium hydroxide amorphous silicon etch method for forming microelectronic capacitor structure 失效
标题翻译：用于形成微电子电容器结构的氢氧化铵水溶液非晶硅蚀刻方法
公开(公告)号：US06881622B2
公开(公告)日：2005-04-19
申请号：US10159226
申请日：2002-05-30
申请人： Chi-Hsing Yu , Chih-Yang Pai , Chia-Shiung Tsai
发明人： Chi-Hsing Yu , Chih-Yang Pai , Chia-Shiung Tsai
IPC分类号： H01L21/02 , H01L21/285 , H01L21/3213 , H01L27/108 , H01L21/8242
CPC分类号： H01L28/60 , H01L21/28525 , H01L21/32134 , H01L27/10811
摘要： Within a method for fabricating a capacitor structure within a microelectronic fabrication there is formed a capacitor structure comprising a pair of capacitor plate layers separated by a capacitor dielectric layer. Within the method, at least one of the pair of capacitor plates is formed of a doped amorphous silicon material formed incident to isotropic etching within an etchant solution comprising aqueous ammonium hydroxide, without hydrogen peroxide.
摘要翻译：在微电子制造中制造电容器结构的方法中，形成了包括由电容器介电层隔开的一对电容器板层的电容器结构。在该方法中，该对电容器板中的至少一个由在不含过氧化氢的含氢氧化铵的蚀刻剂溶液中入射到各向同性蚀刻的掺杂非晶硅材料形成。

60. 发明授权

US06860275B2 Post etching treatment process for high density oxide etcher 失效
标题翻译：高密度氧化蚀刻机的后蚀刻处理工艺
公开(公告)号：US06860275B2
公开(公告)日：2005-03-01
申请号：US10290128
申请日：2002-11-07
申请人： Bao-Ru Young , Chia-Shiung Tsai
发明人： Bao-Ru Young , Chia-Shiung Tsai
IPC分类号： B08B7/00 , H01L21/02 , H01L21/302 , C23F5/00
CPC分类号： H01L21/02063 , B08B7/00
摘要： A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.
摘要翻译：三步聚合物去除方法，其反转除去聚合物的常规顺序。在本发明的优选实施方案中，首先从气体沉积台中除去聚合物，然后从所形成的接触孔的内表面剥离聚合物。

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