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1. 发明授权

US07144773B1 Method for preventing trenching in fabricating split gate flash devices 有权
标题翻译：在制造分闸门闪光装置时防止开沟的方法
公开(公告)号：US07144773B1
公开(公告)日：2006-12-05
申请号：US11141902
申请日：2005-06-01
申请人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H04L21/336 , H04L21/8242 , H04L29/788 , H04L29/76
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521
摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.
摘要翻译：提供了一种用于形成分离栅极闪光装置的方法。在一个实施例中，提供了其上形成介电层的半导体衬底。形成覆盖在电介质层上的导体层。掩蔽层沉积在导体层上。形成覆盖掩模层的光敏层。对感光层进行图案化和蚀刻以在其中形成开口图案。掩模层和导体层根据光敏层中的开口图案进行蚀刻。在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。隔离层填充在多个沟槽和掩蔽层上。掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

2. 发明申请

US20070069328A1 SPLIT GATE FLASH DEVICES 审中-公开
标题翻译：分闸门闪存器件
公开(公告)号：US20070069328A1
公开(公告)日：2007-03-29
申请号：US11555712
申请日：2006-11-02
申请人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521
摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.
摘要翻译：提供了一种用于形成分离栅极闪光装置的方法。在一个实施例中，提供了其上形成介电层的半导体衬底。形成覆盖在电介质层上的导体层。掩蔽层沉积在导体层上。形成覆盖掩模层的光敏层。对感光层进行图案化和蚀刻以在其中形成开口图案。掩模层和导体层根据光敏层中的开口图案进行蚀刻。在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。隔离层填充在多个沟槽和掩蔽层上。掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

3. 发明申请

US20060275984A1 METHOD FOR PREVENTING TRENCHING IN FABRICATING SPLIT GATE FLASH DEVICES 有权
标题翻译：用于防止在制造分离栅格闪存器件中进行TRENCHING的方法
公开(公告)号：US20060275984A1
公开(公告)日：2006-12-07
申请号：US11141902
申请日：2005-06-01
申请人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chi-Hsin Lo , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/115 , H01L27/11521
摘要： A method for forming a split gate flash device is provided. In one embodiment, a semiconductor substrate with a dielectric layer formed thereover is provided. A conductor layer is formed overlying the dielectric layer. A masking layer is deposited overlying the conductor layer. A light sensitive layer is formed overlying the masking layer. The light sensitive layer is patterned and etched to form a pattern of openings therein. The masking layer and the conductor layer are etched according to the pattern of openings in the light sensitive layer. The conductor layer is etched at the outer surface area between the conductor layer and the dielectric layer to form undercuts. The dielectric layer is etched to form a notch profile at the outer surface area between the conductor layer and the dielectric layer and portions of the substrate are etched to form a plurality of trenches. An isolation layer is filled over the plurality of trenches and the masking layer. The masking layer and portions of the conductor layer and isolation layer are etched away, wherein a portion of the isolation layer is preserved in the notch profile.
摘要翻译：提供了一种用于形成分离栅极闪光装置的方法。在一个实施例中，提供了其上形成介电层的半导体衬底。形成覆盖在电介质层上的导体层。掩蔽层沉积在导体层上。形成覆盖掩模层的光敏层。对感光层进行图案化和蚀刻以在其中形成开口图案。掩模层和导体层根据光敏层中的开口图案进行蚀刻。在导体层和电介质层之间的外表面区域处蚀刻导体层以形成底切。蚀刻电介质层以在导体层和电介质层之间的外表面区域形成切口轮廓，并且蚀刻衬底的部分以形成多个沟槽。隔离层填充在多个沟槽和掩蔽层上。掩模层和导体层和隔离层的部分被蚀刻掉，其中隔离层的一部分保留在凹口轮廓中。

4. 发明授权

US08710560B2 Embedded bonding pad for image sensors 有权
标题翻译：用于图像传感器的嵌入式焊盘
公开(公告)号：US08710560B2
公开(公告)日：2014-04-29
申请号：US11835814
申请日：2007-08-08
申请人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L24/05 , H01L27/14636 , H01L2224/05556 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.
摘要翻译：半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

5. 发明申请

US20090039452A1 EMBEDDED BONDING PAD FOR IMAGE SENSORS 有权
标题翻译：用于图像传感器的嵌入式接合垫
公开(公告)号：US20090039452A1
公开(公告)日：2009-02-12
申请号：US11835814
申请日：2007-08-08
申请人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L31/00
CPC分类号： H01L27/14643 , H01L24/05 , H01L27/14636 , H01L2224/05556 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.
摘要翻译：半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

6. 发明授权

US07153755B2 Process to improve programming of memory cells 有权
标题翻译：改善存储单元编程的过程
公开(公告)号：US07153755B2
公开(公告)日：2006-12-26
申请号：US11044813
申请日：2005-01-26
申请人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
发明人： Shih-Chang Liu , Wen-Ting Chu , Chien-Ming Ku , Chi-Hsin Lo , Chia-Shiung Tsai , Chia-Ta Hsieh
IPC分类号： H01L21/762
CPC分类号： H01L27/11521 , H01L21/76224 , H01L27/10894 , H01L27/11
摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.
摘要翻译：提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。该方法包括以下步骤：形成覆盖半导体衬底的表面和STI结构表面的底部抗反射涂层（BARC）层; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

7. 发明授权

US08227850B2 Gated semiconductor device and method of fabricating same 有权
标题翻译：门式半导体器件及其制造方法
公开(公告)号：US08227850B2
公开(公告)日：2012-07-24
申请号：US12723381
申请日：2010-03-12
申请人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
发明人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/6656 , Y10S438/945
摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.
摘要翻译：一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

8. 发明授权

US08114740B2 Profile of flash memory cells 有权
标题翻译：闪存单元简介
公开(公告)号：US08114740B2
公开(公告)日：2012-02-14
申请号：US13045955
申请日：2011-03-11
申请人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

9. 发明授权

US07928499B2 Profile of flash memory cells 有权
标题翻译：闪存单元简介
公开(公告)号：US07928499B2
公开(公告)日：2011-04-19
申请号：US11715229
申请日：2007-03-07
申请人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
发明人： Shih-Chang Liu , Chu-Wei Chang , Chi-Hsin Lo , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L21/28273 , H01L27/11519 , H01L27/11521 , H01L29/42328 , H01L29/7881
摘要： A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的隧道层; 邻近隧道层的源区; 和隧道层上的浮动栅极。浮动门包括具有上部和下部的第一边缘，其中下部从上部凹进。半导体结构还包括在浮置栅极上的阻挡层，其中阻挡层具有面向与浮动栅极的第一边缘相同方向的第一边缘。

10. 发明申请

US20100171167A1 Gated Semiconductor Device and Method of Fabricating Same 有权
标题翻译：门控半导体器件及其制造方法
公开(公告)号：US20100171167A1
公开(公告)日：2010-07-08
申请号：US12723381
申请日：2010-03-12
申请人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
发明人： Shih-Chang Liu , Ming-Hui Shen , Chi-Hsin Lo , Chia-Shiung Tsai , Yi-Shin Chu
IPC分类号： H01L27/088 , H01L21/336 , H01L29/788
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/513 , H01L29/6656 , Y10S438/945
摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.
摘要翻译：一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

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