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51. 发明授权

US06645797B1 Method for forming fins in a FinFET device using sacrificial carbon layer 有权
标题翻译：在使用牺牲碳层的FinFET器件中形成翅片的方法
公开(公告)号：US06645797B1
公开(公告)日：2003-11-11
申请号：US10310926
申请日：2002-12-06
申请人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
发明人： Matthew S. Buynoski , Srikanteswara Dakshina-Murthy , Cyrus E. Tabery , Haihong Wang , Chih-Yuh Yang , Bin Yu
IPC分类号： H01L2184
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.
摘要翻译：一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模。该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

52. 发明授权

US06555879B1 SOI device with metal source/drain and method of fabrication 有权
标题翻译：具有金属源/漏极的SOI器件及其制造方法
公开(公告)号：US06555879B1
公开(公告)日：2003-04-29
申请号：US10044247
申请日：2002-01-11
申请人： Zoran Krivokapic , Qi Xiang , Bin Yu
发明人： Zoran Krivokapic , Qi Xiang , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.
摘要翻译：一种MOSFET及其制造方法。 MOSFET包括含金属源和含金属的漏极; 设置在源极和漏极之间并且在绝缘层的顶部上具有小于约15nm的厚度的半导体本体，所述绝缘层形成在基板上; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。

53. 发明授权

US06555437B1 Multiple halo implant in a MOSFET with raised source/drain structure 有权
标题翻译：具有升高的源极/漏极结构的MOSFET中的多个晕轮注入
公开(公告)号：US06555437B1
公开(公告)日：2003-04-29
申请号：US09844888
申请日：2001-04-27
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/26586 , H01L29/1083 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/66628
摘要： A method and device for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves forming a multi-graded lateral channel doping profile by dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of 50 nm or less. The method includes forming a spacer on the sidewalls of a gate, followed by forming source/drain regions by epitaxial growth followed by a deep source/drain implant and anneal. After removal of the spacer, the first angled deep halo implant through the space formed by removal of the spacer and a second annealing at a temperature lower than the first anneal occurs. A second angled halo implant and a third anneal at a temperature less than the second anneal is performed. The microelectronic chip is then silicided and the MOSFET is further completed.
摘要翻译：一种用于改善深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法和装置。该方法包括通过在不同温度下退火的双光晕植入物形成多梯度横向沟道掺杂分布，以改善50nm或更小的MOSFET的阈值电压滚降特性。该方法包括在栅极的侧壁上形成间隔物，随后通过外延生长随后进行深源极/漏极注入和退火来形成源极/漏极区域。在去除间隔物之后，通过去除间隔物形成的空间的第一倾斜的深晕注入和在低于第一退火的温度下进行第二次退火。执行第二倾斜的晕轮植入物和在小于第二退火的温度下的第三退火。然后将微电子芯片硅化并且MOSFET进一步完成。

54. 发明授权

US06521502B1 Solid phase epitaxy activation process for source/drain junction extensions and halo regions 有权
标题翻译：用于源极/漏极结延伸部分和晕圈区域的固相外延激活过程
公开(公告)号：US06521502B1
公开(公告)日：2003-02-18
申请号：US09633207
申请日：2000-08-07
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2100
CPC分类号： H01L29/6659 , H01L21/2022 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083
摘要： A method of manufacturing an integrated circuit may include the steps of forming a deep amorphous region and doping the deep amorphous region. The doping of the deep amorphous region can form source and drain regions with extensions. After doping, the substrate is annealed. The annealing can occur at a low temperature.
摘要翻译：制造集成电路的方法可以包括形成深非晶区域并掺杂深非晶区域的步骤。深非晶区域的掺杂可以形成具有延伸的源极和漏极区域。掺杂后，将基板退火。退火可以在低温下进行。

55. 发明授权

US06514829B1 Method of fabricating abrupt source/drain junctions 有权
标题翻译：制造突发性源极/漏极结的方法
公开(公告)号：US06514829B1
公开(公告)日：2003-02-04
申请号：US09803831
申请日：2001-03-12
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L21/26586 , H01L29/458 , H01L29/78684
摘要： A method of fabricating an integrated circuit forming abrupt source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs) on a silicon-on-insulator (SOI) substrate. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.
摘要翻译：一种形成突发的源极/漏极结的集成电路的方法。该工艺可用于绝缘体上硅（SOI）衬底上的P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。源极延伸比漏极延伸更为导电。晶体管减少了短沟道效应和强大的驱动电流，而且可靠。

56. 发明授权

US06506650B1 Method of fabrication based on solid-phase epitaxy for a MOSFET transistor with a controlled dopant profile 有权
标题翻译：基于具有受控掺杂物分布的MOSFET晶体管的固相外延制造方法
公开(公告)号：US06506650B1
公开(公告)日：2003-01-14
申请号：US09843782
申请日：2001-04-27
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L21/26506 , H01L21/2652 , H01L29/6656 , H01L29/6659
摘要： A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer having reduced height “cutouts” adjacent to the gate stack. The L-shaped spacer is preferably created by depositing two layers of insulating material, over which a third spacer is formed as a mask for removing unwanted portions of the first and second insulation layers. Amorphization and deep implantation is performed through the L-shaped spacer, wherein the junction contour is profiled in response to the geometry of the L-shaped spacer, such that a single deep implantation step may be utilized. Pocketed steps within the contoured junction reduce short-channel effects while allowing the formation of silicide to a depth which exceeds the junction depth implanted beneath the gate electrode.
摘要翻译：描述了一种MOSFET晶体管及其制造方法，用于通过单个深度注入步骤和固相外延来在MOSFET晶体管内工程化沟道掺杂物分布。该方法利用形成邻近栅极叠层的具有减小的高度“切口”的L形间隔物。优选地，通过沉积两层绝缘材料来形成L形间隔件，在其上形成第三间隔件作为掩模，以去除第一和第二绝缘层的不期望的部分。通过L形间隔件执行非晶化和深度注入，其中响应于L形间隔件的几何形状，连接轮廓被成型，使得可以利用单个深度注入步骤。轮廓结中的凹槽可以减少短沟道效应，同时允许硅化物的形成深度超过浇注在栅电极下方的结深度。

57. 发明授权

US06506638B1 Vertical double gate transistor structure 失效
标题翻译：垂直双栅晶体管结构
公开(公告)号：US06506638B1
公开(公告)日：2003-01-14
申请号：US09689063
申请日：2000-10-12
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L2100
CPC分类号： H01L29/66666 , H01L29/7827
摘要： A method of manufacturing a vertical transistor. The vertical transistor utilizes a deposited amorphous silicon layer to form a source region. The vertical gate transistor includes a double gate structure for providing increased drive current. A wafer bonding technique can be utilized to form the substrate.
摘要翻译：一种垂直晶体管的制造方法。垂直晶体管利用沉积的非晶硅层形成源区。垂直栅极晶体管包括用于提供增加的驱动电流的双栅极结构。可以利用晶片接合技术来形成衬底。

58. 发明授权

US06495402B1 Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture 有权
标题翻译：具有源极/漏极硅锗区域的绝缘体上半导体（SOI）器件及其制造方法
公开(公告)号：US06495402B1
公开(公告)日：2002-12-17
申请号：US09777637
申请日：2001-02-06
申请人： Bin Yu , Ralf van Bentum
发明人： Bin Yu , Ralf van Bentum
IPC分类号： H01L2100
CPC分类号： H01L29/66477 , H01L21/26506 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/78618 , H01L29/78684
摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer, the active layer having an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween, each of the source and the drain having a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon, the silicon-germanium regions forming heterojunction portions respectively along the source/body junction and the drain/body junction. A method of fabricating the SOI device is also disclosed.
摘要翻译：绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层，该有源层具有由隔离区域限定的有源区域，该有源区域具有源极和漏极，其间设置有一个主体源极和漏极中的每一个具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层之下，硅 - 锗区域分别沿着源极/主体结和漏极/本体结形成异质结部分。还公开了制造SOI器件的方法。

59. 发明授权

US06482705B1 Method of fabricating a semiconductor device having a MOSFET with an amorphous SiGe gate electrode and an elevated crystalline SiGe source/drain structure and a device thereby formed 有权
标题翻译：制造具有非晶SiGe栅电极和升高的晶体SiGe源极/漏极结构的MOSFET的半导体器件的方法和由此形成的器件
公开(公告)号：US06482705B1
公开(公告)日：2002-11-19
申请号：US09825659
申请日：2001-04-03
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/2807 , H01L29/41783 , H01L29/4966 , H01L29/665
摘要： A method of fabricating a semiconductor device, having a MOSFET with an amorphous-silicon-germanium gate electrode and an elevated crystalline silicon-germanium source/drain structure for preventing adverse reaction with an underlying silicon substrate, and a device thereby formed. The gate electrode and the raised S/D structure are simultaneously formed by depositing and polishing an amorphous-silicon-germanium film and subsequently heating the polished an amorphous-silicon-germanium film in a low temperature range. Generally, the method involves: (1) depositing an amorphous-silicon-germanium layer; (2) simultaneously forming a raised source/drain structure and a gate electrode by polishing the amorphous-silicon-germanium layer; and (3) annealing the raised source/drain structure and a gate electrode.
摘要翻译：一种制造半导体器件的方法，其具有具有非晶硅锗锗栅极的MOSFET和用于防止与下面的硅衬底的不利反应的升高的晶体硅 - 锗源极/漏极结构以及由此形成的器件。通过沉积和抛光非晶硅 - 锗膜并随后在低温范围内加热抛光的非晶硅 - 锗膜，同时形成栅电极和升高的S / D结构。通常，该方法包括：（1）沉积非晶硅 - 锗层; （2）通过抛光非晶硅 - 锗层同时形成升高的源/漏结构和栅电极; 和（3）对升高的源极/漏极结构和栅电极进行退火。

60. 发明授权

US06468888B1 Method for forming polysilicon-germanium gate in CMOS transistor and device made thereby 失效
标题翻译：在CMOS晶体管中形成多晶硅 - 锗栅的方法及其制造的器件
公开(公告)号：US06468888B1
公开(公告)日：2002-10-22
申请号：US09685974
申请日：2000-10-10
申请人： Bin Yu
发明人： Bin Yu
IPC分类号： H01L213205
CPC分类号： H01L29/4966 , H01L21/2807 , H01L21/32105 , H01L21/32155 , H01L21/823828
摘要： A method for making a ULSI MOSFET chip includes forming transistor gates on a substrate and a semiconductor device thereby made. The gates are formed by depositing a polysilicon layer on the substrate, implanting germanium into the polysilicon layer at a comparatively low dose, and then oxidizing the doped polysilicon layer. Under the influence of the oxidation, the germanium is repelled from an upper sacrificial region of the polysilicon layer into a lower gate region of the polysilicon layer, thereby increasing the germanium concentration in the lower gate region. The sacrificial region is then etched away and an undoped polysilicon film deposited on the gate region. Subsequently, the gate region with undoped polysilicon film is patterned to establish a MOSFET gate, with the substrate then being appropriately processed to establish MOSFET source/drain regions.
摘要翻译：制造ULSI MOSFET芯片的方法包括在衬底上形成晶体管栅极和由此制成的半导体器件。栅极通过在衬底上沉积多晶硅层，以比较低的剂量将锗注入到多晶硅层中，然后氧化掺杂的多晶硅层而形成。在氧化的影响下，锗从多晶硅层的上部牺牲区域排斥到多晶硅层的下部栅极区域，从而增加下部栅极区域中的锗浓度。然后蚀刻掉牺牲区域，并且在栅极区域上沉积未掺杂的多晶硅膜。随后，对具有未掺杂多晶硅膜的栅极区域进行构图以建立MOSFET栅极，然后适当地处理衬底以建立MOSFET源极/漏极区域。

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