专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US07379336B2 Integrated DRAM-NVRAM multi-level memory 有权
公开(公告)号：US07379336B2
公开(公告)日：2008-05-27
申请号：US11367860
申请日：2006-03-03
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： G11C11/34
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

52. 发明申请

US20080087945A1 SILICON LANTHANIDE OXYNITRIDE FILMS 有权
标题翻译：硅氧烷氧化物膜
公开(公告)号：US20080087945A1
公开(公告)日：2008-04-17
申请号：US11514533
申请日：2006-08-31
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/8242 , H01L29/792
CPC分类号： H01L29/518 , C23C16/308 , C23C16/34 , C23C16/345 , C23C16/40 , C23C16/45529 , C23C16/45531 , C23C16/56 , H01L21/02156 , H01L21/0228 , H01L21/02326 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28079 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L21/3142 , H01L21/3145 , H01L21/31608 , H01L28/65 , H01L29/495 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/66545 , H01L29/7881
摘要： Electronic apparatus and methods of forming the electronic apparatus include a silicon lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The silicon lanthanide oxynitride film may be arranged as a layered structure having one or more monolayers. Metal electrodes may be disposed on a dielectric containing a silicon lanthanide oxynitride film.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的基板上的镧系元素氧氮化硅膜。硅镧系氮氧化物膜可以配置为具有一个或多个单层的层状结构。金属电极可以设置在含有镧系元素氮氧化物膜的电介质上。

53. 发明授权

US07158410B2 Integrated DRAM-NVRAM multi-level memory 有权
标题翻译：集成DRAM-NVRAM多级存储器
公开(公告)号：US07158410B2
公开(公告)日：2007-01-02
申请号：US10928250
申请日：2004-08-27
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： G11C11/34
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.
摘要翻译：集成的DRAM-NVRAM，多级存储单元由具有共享垂直门浮板器件的垂直DRAM器件组成。浮置板装置通过两个功能之间的支柱中的共享浮体为单元的DRAM部分提供增强的电荷存储。存储单元形成在具有形成支柱的沟槽的基板中。柱的一侧的垂直字线/栅极用于控制单元的DRAM部分。在柱的另一侧上的垂直捕获层存储一个或多个电荷作为浮置板装置的一部分，并且通过DRAM和浮动板装置之间的浮体增强DRAM功能。垂直NVRAM字线/控制栅极与俘获层一起形成，并与相邻的浮置板装置共享。

54. 发明申请

US20060176726A1 Integrated DRAM-NVRAM multi-level memory 失效
标题翻译：集成DRAM-NVRAM多级存储器
公开(公告)号：US20060176726A1
公开(公告)日：2006-08-10
申请号：US11368180
申请日：2006-03-03
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： G11C11/24
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.
摘要翻译：集成的DRAM-NVRAM，多级存储单元由具有共享垂直门浮板器件的垂直DRAM器件组成。浮置板装置通过两个功能之间的支柱中的共享浮体为单元的DRAM部分提供增强的电荷存储。存储单元形成在具有形成支柱的沟槽的基板中。柱的一侧的垂直字线/栅极用于控制单元的DRAM部分。在柱的另一侧上的垂直捕获层存储一个或多个电荷作为浮置板装置的一部分，并且通过DRAM和浮动板装置之间的浮体增强DRAM功能。垂直NVRAM字线/控制栅极与俘获层一起形成，并与相邻的浮置板装置共享。

55. 发明申请

US20060146606A1 Integrated DRAM-NVRAM multi-level memory 失效
公开(公告)号：US20060146606A1
公开(公告)日：2006-07-06
申请号：US11367925
申请日：2006-03-03
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： G11C14/00 , G11C16/04
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

56. 发明申请

US20060145246A1 Integrated DRAM-NVRAM multi-level memory 有权
公开(公告)号：US20060145246A1
公开(公告)日：2006-07-06
申请号：US11368037
申请日：2006-03-03
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： H01L31/113 , H01L29/94 , H01L29/788
CPC分类号： G11C14/00 , G11C11/5621 , G11C11/5671 , G11C14/0018
摘要： An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

57. 发明授权

US08294224B2 Devices and methods to improve carrier mobility 有权
标题翻译：改善载波移动性的装置和方法
公开(公告)号：US08294224B2
公开(公告)日：2012-10-23
申请号：US11398809
申请日：2006-04-06
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： H01L21/31 , H01L21/469 , H01L21/02
CPC分类号： H01L21/0214 , H01L21/02271 , H01L21/0228 , H01L21/28282 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/823807 , H01L21/823864 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L29/1054 , H01L29/6659 , H01L29/66833 , H01L29/7833 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的半导体器件上的氮氧化硅层。氧氮化硅层可以被构造为控制半导体器件的硅沟道中的应变以改善硅沟道中的载流子迁移率，其中硅沟道被配置为在半导体器件的合适的工作条件下传导电流。

58. 发明授权

US08293611B2 Implantation processes for straining transistor channels of semiconductor device structures and semiconductor devices with strained transistor channels 有权
标题翻译：具有应变晶体管沟道的半导体器件结构和半导体器件的应变晶体管沟道的植入过程
公开(公告)号：US08293611B2
公开(公告)日：2012-10-23
申请号：US11745814
申请日：2007-05-08
申请人： Arup Bhattacharyya , Leonard Forbes , Paul A Farrar
发明人： Arup Bhattacharyya , Leonard Forbes , Paul A Farrar
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , B82Y10/00 , H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/66492 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
摘要翻译：本发明包括用于应力半导体器件结构的晶体管沟道的方法。这种方法包括形成邻近源极/漏极区域的所谓近表面纳米孔，形成邻近并包括纳米孔的源极/漏极区域的延伸部分，以及将扩大或收缩体积的类型的植入物质分别取决于在NMOS场效应晶体管中如在NMOS场效应晶体管中在纳米腔中的晶体管通道中是否需要压缩应变，如在PMOS场效应晶体管中的拉伸应变或拉伸应变，以增强载流子迁移率和晶体管速度。还公开了包括这些特征的半导体器件结构和半导体器件。

59. 发明申请

US20120094477A1 HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC 有权
标题翻译：高压氧化铝电介质
公开(公告)号：US20120094477A1
公开(公告)日：2012-04-19
申请号：US13332222
申请日：2011-12-20
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/28
CPC分类号： G11C16/0466 , H01L21/3142 , H01L21/31637 , H01L21/31645 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66545
摘要： Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
摘要翻译：电子设备和方法可以包括用于各种电子系统的基板上的铪钽氮化物膜。铪钽氮氧化物膜可以被构造为一个或多个单层。可以使用原子层沉积形成氮氧化钽铪膜。金属电极可以设置在含有铪钽氮氧化物膜的电介质上。

60. 发明授权

US07902582B2 Tantalum lanthanide oxynitride films 有权
标题翻译：钽镧系氮氧化物薄膜
公开(公告)号：US07902582B2
公开(公告)日：2011-03-08
申请号：US12470121
申请日：2009-05-21
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/00
CPC分类号： H01L21/02194 , C23C14/20 , C23C16/308 , C23C16/34 , C23C16/40 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/022 , H01L21/0228 , H01L21/02326 , H01L21/02332 , H01L21/0234 , H01L21/28202 , H01L21/3141 , H01L21/3142 , H01L21/31637 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的基板上的钽镧系元素氮氧化物膜。钽镧系氮氧化物膜可以被构造为一个或多个单层。金属电极可以设置在包含钽镧系元素氮氧化物膜的电介质上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式