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51. 发明申请

US20110140167A1 Nanotube Semiconductor Devices 有权
标题翻译：纳米管半导体器件
公开(公告)号：US20110140167A1
公开(公告)日：2011-06-16
申请号：US13024256
申请日：2011-02-09
申请人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
发明人： Hamza Yilmaz , Xiaobin Wang , Anup Bhalla , John Chen , Hong Chang
IPC分类号： H01L29/739 , H01L21/331
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0692 , H01L29/1095 , H01L29/6609 , H01L29/66143 , H01L29/66348 , H01L29/66666 , H01L29/7397 , H01L29/861 , H01L29/872
摘要： A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.
摘要翻译：形成半导体器件的方法包括：使用形成在半导体本体中的沟槽的侧壁上的薄外延层来形成纳米管区域。薄的外延层具有均匀的掺杂浓度。在另一个实施例中，在半导体主体中的沟槽的侧壁上形成与半导体本体相同的导电类型的第一薄外延层，并且在第一外延层上形成相反导电类型的第二薄外延层。第一和第二外延层具有均匀的掺杂浓度。选择第一和第二外延层和半导体本体的厚度和掺杂浓度以实现电荷平衡。在一个实施例中，半导体本体是轻掺杂的P型衬底。可以使用相同的N-Epi / P-Epi纳米管结构形成垂直沟槽MOSFET，IGBT，肖特基二极管和P-N结二极管。

52. 发明申请

US20090127593A1 MOS device 有权
标题翻译： MOS器件
公开(公告)号：US20090127593A1
公开(公告)日：2009-05-21
申请号：US12228142
申请日：2008-08-07
申请人： Anup Bhalla , Xiaobin Wang
发明人： Anup Bhalla , Xiaobin Wang
IPC分类号： H01L21/338 , H01L29/812
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0623 , H01L29/1095 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device includes a drain, an epitaxial layer overlaying the drain, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, the active region contact trench having a varying contact trench depth, and an active region contact electrode disposed within the active region contact trench.
摘要翻译：半导体器件包括漏极，覆盖漏极的外延层，设置在外延层中的主体，嵌入在主体中的源极，延伸到外延层中的栅极沟槽，设置在栅极沟槽中的栅极，有源区域触点延伸穿过源极的沟槽，具有变化的接触沟槽深度的有源区接触沟槽和设置在有源区接触沟槽内的有源区接触电极。

53. 发明申请

US20090065861A1 MOS device with low injection diode 有权
标题翻译：具有低注入二极管的MOS器件
公开(公告)号：US20090065861A1
公开(公告)日：2009-03-12
申请号：US12005130
申请日：2007-12-21
申请人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
发明人： Anup Bhalla , Xiaobin Wang , Ji Pan , Sung-Po Wei
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1095 , H01L21/26586 , H01L29/0623 , H01L29/165 , H01L29/41766 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： A semiconductor device is formed on a semiconductor substrate. The device includes a drain, an epitaxial layer overlaying the drain, and an active region. The active region includes a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and into the body, an active region contact electrode disposed within the active region contact trench, wherein a thin layer of body region separating the active region contact electrode from the drain.
摘要翻译：半导体器件形成在半导体衬底上。该器件包括漏极，覆盖漏极的外延层和有源区。所述有源区包括设置在所述外延层中的主体，具有主体顶表面，嵌入在所述主体中的源，从所述主体顶表面延伸到所述主体中，延伸到所述外延层中的栅沟槽，设置在所述栅极中的栅极沟槽，延伸穿过源极并进入主体的有源区接触沟槽，设置在有源区接触沟槽内的有源区接触电极，其中将有源区接触电极与漏极分离的体区的薄层。

54. 发明授权

US10468526B2 Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method 有权
公开(公告)号：US10468526B2
公开(公告)日：2019-11-05
申请号：US15836756
申请日：2017-12-08
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/265 , H01L29/417 , H01L29/45 , H01L29/47 , H01L29/08
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

55. 发明申请

US20180138906A9 ROBUST SEMICONDUCTOR POWER DEVICES WITH DESIGN TO PROTECT TRANSISTOR CELLS WITH SLOWER SWITCHING SPEED 审中-公开
公开(公告)号：US20180138906A9
公开(公告)日：2018-05-17
申请号：US14585201
申请日：2014-12-30
申请人： Sik K. Lui , Anup Bhalla
发明人： Sik K. Lui , Anup Bhalla
IPC分类号： H03K17/687 , H01H49/00
CPC分类号： H01H49/00 , H01L29/0696 , H01L29/0856 , H01L29/086 , H01L29/7803 , H01L29/7813 , H01L2924/0002 , H03K17/04123 , H03K17/08122 , H03K17/122 , H03K17/164 , H03K17/687 , Y10T29/49105 , Y10T307/747 , Y10T307/76 , H01L2924/00
摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.

56. 发明申请

US20180102435A1 SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD 审中-公开
公开(公告)号：US20180102435A1
公开(公告)日：2018-04-12
申请号：US15836756
申请日：2017-12-08
申请人： François Hébert , Madjur Bobde , Anup Bhalla
发明人： François Hébert , Madjur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7828 , H01L21/26586 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66666 , H01L29/7806
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

57. 发明申请

US20170288034A1 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
公开(公告)号：US20170288034A1
公开(公告)日：2017-10-05
申请号：US15499487
申请日：2017-04-27
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/423 , H01L29/06 , H01L29/40 , H01L27/088
CPC分类号： H01L29/42368 , H01L27/088 , H01L29/0619 , H01L29/401 , H01L29/4236
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

58. 发明申请

US20170213887A1 INTEGRATED SCHOTTKY DIODE IN HIGH VOLTAGE SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170213887A1
公开(公告)日：2017-07-27
申请号：US15479281
申请日：2017-04-05
申请人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
发明人： Lingpeng Guan , Anup Bhalla , Madhur Bobde , Tinggang Zhu
IPC分类号： H01L29/06 , H01L29/78 , H01L29/10 , H01L29/739 , H01L29/49 , H01L29/872
CPC分类号： H01L29/0634 , H01L29/0619 , H01L29/0834 , H01L29/1095 , H01L29/404 , H01L29/42368 , H01L29/4916 , H01L29/512 , H01L29/66333 , H01L29/66712 , H01L29/7393 , H01L29/7395 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions and e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions.

59. 发明授权

US09685523B2 Diode structures with controlled injection efficiency for fast switching 有权
公开(公告)号：US09685523B2
公开(公告)日：2017-06-20
申请号：US14573187
申请日：2014-12-17
申请人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
发明人： Madhur Bobde , Harsh Naik , Lingpeng Guan , Anup Bhalla , Sik Lui
IPC分类号： H01L29/868 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/40 , H01L29/739
CPC分类号： H01L29/868 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/36 , H01L29/402 , H01L29/407 , H01L29/6609 , H01L29/66136 , H01L29/66143 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7803 , H01L29/7839 , H01L29/861 , H01L29/8613 , H01L29/8725
摘要： This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

60. 发明申请

US20160191048A1 ROBUST SEMICONDUCTOR POWER DEVICES WITH DESIGN TO PROTECT TRANSISTOR CELLS WITH SLOWER SWITCHING SPEED 审中-公开
标题翻译：设计用于保护具有滑动开关速度的晶体管电池的稳定的半导体电源器件
公开(公告)号：US20160191048A1
公开(公告)日：2016-06-30
申请号：US14585201
申请日：2014-12-30
申请人： Sik K. Lui , Anup Bhalla
发明人： Sik K. Lui , Anup Bhalla
IPC分类号： H03K17/687 , H01H49/00
CPC分类号： H01H49/00 , H01L29/0696 , H01L29/0856 , H01L29/086 , H01L29/7803 , H01L29/7813 , H01L2924/0002 , H03K17/04123 , H03K17/08122 , H03K17/122 , H03K17/164 , H03K17/687 , Y10T29/49105 , Y10T307/747 , Y10T307/76 , H01L2924/00
摘要： This invention discloses a power switch that includes a fast-switch semiconductor power device and a slow-switch semiconductor power device controllable to turn on and off a current transmitting therethrough. The slow-switch semiconductor power device further includes a ballasting resistor for increasing a device robustness of the slow switch semiconductor power device. In an exemplary embodiment, the fast-switch semiconductor power device includes a fast switch metal oxide semiconductor field effect transistor (MOSFET) and the slow-switch semiconductor power device includes a slow switch MOSFET wherein the slow switch MOSFET further includes a source ballasting resistor.
摘要翻译：本发明公开了一种功率开关，其包括快速开关半导体功率器件和可控制的开关半导体功率器件，用于接通和断开通过其传输的电流。慢开关半导体功率器件还包括用于增加慢开关半导体功率器件的器件鲁棒性的镇流电阻器。在示例性实施例中，快速切换半导体功率器件包括快速开关金属氧化物半导体场效应晶体管（MOSFET），而慢开关半导体功率器件包括慢开关MOSFET，其中慢开关MOSFET还包括源极镇流电阻器。

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