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51. 发明申请

US20070224399A1 THICK POROUS ANODIC ALUMINA FILMS AND NANOWIRE ARRAYS GROWN ON A SOLID SUBSTRATE 失效
标题翻译：厚多孔阳极氧化铝膜和固体基底上的纳米阵列
公开(公告)号：US20070224399A1
公开(公告)日：2007-09-27
申请号：US10303653
申请日：2002-11-25
申请人： Oded Rabin , Paul Herz , Mildred Dresselhaus , Akintunde Akinwande , Yu-Ming Lin
发明人： Oded Rabin , Paul Herz , Mildred Dresselhaus , Akintunde Akinwande , Yu-Ming Lin
IPC分类号： B32B3/00
CPC分类号： C23C14/024 , B82Y30/00 , C23C14/16 , C23C14/5873 , C30B7/00 , C30B7/005 , C30B29/605 , H01L35/32 , H01L35/34 , Y10T156/10 , Y10T428/12486 , Y10T428/1259 , Y10T428/24273 , Y10T428/24322 , Y10T428/24917
摘要： The presently disclosed invention provides for the fabrication of porous anodic alumina (PAA) films on a wide variety of substrates. The substrate comprises a wafer layer and may further include an adhesion layer deposited on the wafer layer. An anodic alumina template is formed on the substrate. When a rigid substrate such as Si is used, the resulting anodic alumina film is more tractable, easily grown on extensive areas in a uniform manner, and manipulated without danger of cracking. The substrate can be manipulated to obtain free-standing alumina templates of high optical quality and substantially flat surfaces PAA films can also be grown this way on patterned and non-planar surfaces. Furthermore, under certain conditions the resulting PAA is missing the barrier layer (partially or completely) and the bottom of the pores can be readily accessed electrically. The resultant film can be used as a template for forming an array of nanowires wherein the nanowires are deposited electrochemically into the pores of the template. By patterning the electrically conducting adhesion layer, pores in different areas of the template can be addressed independently, and can be filled electrochemically by different materials. Single-stage and multi-stage nanowire-based thermoelectric devices, consisting of both n-type and p-type nanowires, can be assembled on a silicon substrate by this method
摘要翻译：目前公开的发明提供了在各种基底上制造多孔阳极氧化铝（PAA）膜。衬底包括晶片层，并且还可以包括沉积在晶片层上的粘附层。在基板上形成阳极氧化铝模板。当使用诸如Si的刚性基材时，所得的阳极氧化铝膜更易于处理，容易在均匀的方式在广泛的区域生长，并且操作而没有开裂的危险。可以操作基底以获得高光学质量的自立式氧化铝模板和基本平坦的表面。也可以在图案化和非平面表面上生长PAA膜。此外，在某些条件下，所得PAA缺少阻挡层（部分或完全），并且孔的底部可以容易地电接触。所得膜可以用作形成纳米线阵列的模板，其中纳米线电化学沉积到模板的孔中。通过图案化导电粘合层，可以独立地解决模板的不同区域中的孔，并且可以通过不同的材料电化学填充。由n型和p型纳米线组成的单级和多级纳米线型热电装置可以通过这种方法组装在硅衬底上

52. 发明申请

US20070048908A1 METHOD AND APPARATUS FOR FABRICATING A CARBON NANOTUBE TRANSISTOR 失效
标题翻译：制备碳纳米管晶体的方法和装置
公开(公告)号：US20070048908A1
公开(公告)日：2007-03-01
申请号：US11553331
申请日：2006-10-26
申请人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
发明人： Joerg Appenzeller , Phaedon Avouris , Yu-Ming Lin
IPC分类号： H01L21/8232
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , Y10S977/721
摘要： A method of fabricating a nanotube field-effect transistor having unipolar characteristics and a small inverse sub-threshold slope includes forming a local gate electrode beneath the nanotube between drain and source electrodes of the transistor and doping portions of the nanotube. In a further embodiment, the method includes forming at least one trench in the gate dielectric (e.g., a back gate dielectric) and back gate adjacent to the local gate electrode. Another aspect of the invention is a nanotube field-effect transistor fabricated using such a method.
摘要翻译：一种制造具有单极特性和小的反向亚阈值斜率的纳米管场效应晶体管的方法包括在晶体管的漏极和源极之间的纳米管下面形成局部栅电极，并掺杂纳米管的部分。在另一实施例中，该方法包括在栅极电介质（例如，背栅极电介质）中形成至少一个沟槽和邻近局部栅电极的后栅极。本发明的另一方面是使用这种方法制造的纳米管场效应晶体管。

53. 发明授权

US08926853B2 Graphene structures with enhanced stability and composite materials formed therefrom 有权
标题翻译：具有增强的稳定性的石墨烯结构和由其形成的复合材料
公开(公告)号：US08926853B2
公开(公告)日：2015-01-06
申请号：US13592370
申请日：2012-08-23
申请人： Xin Zhao , Yu-Ming Lin
发明人： Xin Zhao , Yu-Ming Lin
IPC分类号： B44C1/22 , B05D3/10
CPC分类号： H01M4/133 , B82Y30/00 , H01M4/96 , H01M8/04216 , H01M10/0525 , Y10T29/49115 , Y10T29/49885 , Y10T428/30
摘要： Aspects of the invention are directed to a method of forming graphene structures. Initially, a cluster of particles is received. The cluster of particles comprises a plurality of particles with each particle in the plurality of particles contacting one or more other particles in the plurality of particles. Subsequently, one or more layers are deposited on the cluster of particles with the one or more layers comprising graphene. The plurality of particles are then etched away without substantially etching the deposited one or more layers. Lastly, the remaining one or more layers are dried. The resultant graphene structures are particularly resistant to the negative effects of aggregation and compaction.
摘要翻译：本发明的方面涉及形成石墨烯结构的方法。最初，接收到一群粒子。颗粒簇包括多个颗粒，多个颗粒中的每个颗粒与多个颗粒中的一个或多个其它颗粒接触。随后，一层或多层沉积在颗粒簇上，其中一层或多层包含石墨烯。然后蚀刻掉多个颗粒，而基本上不蚀刻沉积的一个或多个层。最后，将剩余的一层或多层干燥。所得到的石墨烯结构特别抵抗聚集和压实的负面影响。

54. 发明授权

US08803130B2 Graphene transistors with self-aligned gates 有权
标题翻译：具有自对准栅极的石墨烯晶体管
公开(公告)号：US08803130B2
公开(公告)日：2014-08-12
申请号：US13492097
申请日：2012-06-08
申请人： Ali Afzali-Ardakani , Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
发明人： Ali Afzali-Ardakani , Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
IPC分类号： H01L29/06
CPC分类号： H01L29/1606 , H01L29/42376 , H01L29/66431 , H01L29/7781 , Y10S977/734
摘要： Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.
摘要翻译：公开了石墨烯晶体管器件及其制造方法。一种这样的石墨烯晶体管器件包括源电极和漏电极以及包括设置在源极和漏极之间的电介质侧壁间隔物的栅极结构。该器件还包括与源极和漏极电极中的至少一个相邻的石墨烯层，其中源/漏电极和石墨烯层之间的界面在整个界面处保持一致的电导率。

55. 发明申请

US20140060726A1 METHODS FOR TRANSFERRING GRAPHENE FILMS AND THE LIKE BETWEEN SUBSTRATES 审中-公开
标题翻译：用于传输石墨膜的方法和基板之间的类似
公开(公告)号：US20140060726A1
公开(公告)日：2014-03-06
申请号：US13603786
申请日：2012-09-05
申请人： Yijing Yin Stehle , Xuesong Li , Yu-Ming Lin , Chun-Yung Sung
发明人： Yijing Yin Stehle , Xuesong Li , Yu-Ming Lin , Chun-Yung Sung
IPC分类号： B32B38/10 , B82Y40/00
CPC分类号： B32B37/26 , B32B2037/268 , B32B2457/00 , B82Y40/00
摘要： Aspects of the invention are directed to a method of forming a thin film adhered to a target substrate. The method comprises the steps of: (i) forming the thin film on a deposition substrate; (ii) depositing a support layer on the thin film; (iii) removing the deposition substrate without substantially removing the thin film and the support layer; (iv) drying the thin film and the support layer while the thin film is only adhered to the support layer; (v) placing the dried thin film and the dried support layer on the target substrate such that the thin film adheres to the target substrate; and (vi) removing the support layer without substantially removing the thin film and the target substrate.
摘要翻译：本发明的方面涉及一种形成粘附到目标基底上的薄膜的方法。该方法包括以下步骤：（i）在沉积衬底上形成薄膜; （ii）在薄膜上沉积支撑层; （iii）除去沉积基板，而基本不除去薄膜和支撑层; （iv）在薄膜仅粘附到支撑层的同时干燥薄膜和支撑层; （v）将干燥的薄膜和干燥的支撑层放置在目标基板上，使得薄膜粘附到目标基板; 和（vi）除去支撑层而基本上不去除薄膜和目标基底。

56. 发明申请

US20130299782A1 GRAPHENE TRANSISTORS WITH SELF-ALIGNED GATES 有权
标题翻译：具有自对准栅的石墨晶体管
公开(公告)号：US20130299782A1
公开(公告)日：2013-11-14
申请号：US13492097
申请日：2012-06-08
申请人： ALI AFZALI-ARDAKANI , PHAEDON AVOURIS , DAMON B. FARMER , YU-MING LIN , YU ZHU
发明人： ALI AFZALI-ARDAKANI , PHAEDON AVOURIS , DAMON B. FARMER , YU-MING LIN , YU ZHU
IPC分类号： H01L29/772 , B82Y99/00
CPC分类号： H01L29/1606 , H01L29/42376 , H01L29/66431 , H01L29/7781 , Y10S977/734
摘要： Graphene transistor devices and methods of their fabrication are disclosed. One such graphene transistor device includes source and drain electrodes and a gate structure including a dielectric sidewall spacer that is disposed between the source and drain electrodes. The device further includes a graphene layer that is adjacent to at least one of the source and drain electrodes, where an interface between the source/drain electrode(s) and the graphene layer maintains a consistent degree of electrical conductivity throughout the interface.
摘要翻译：公开了石墨烯晶体管器件及其制造方法。一种这样的石墨烯晶体管器件包括源电极和漏电极以及包括设置在源极和漏极之间的电介质侧壁间隔物的栅极结构。该器件还包括与源极和漏极电极中的至少一个相邻的石墨烯层，其中源/漏电极和石墨烯层之间的界面在整个界面处保持一致的电导率。

57. 发明申请

US20130207080A1 BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES 失效
标题翻译：用于石墨设备的低等效氧化物厚度的双层栅介质
公开(公告)号：US20130207080A1
公开(公告)日：2013-08-15
申请号：US13369901
申请日：2012-02-09
申请人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
发明人： Christos D. Dimitrakopoulos , Damon B. Farmer , Alfred Grill , Yu-Ming Lin , Deborah A. Neumayer , Dirk Pfeiffer , Wenjuan Zhu
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L21/0237 , B82Y30/00 , B82Y40/00 , H01L21/02378 , H01L21/02527 , H01L21/02617 , H01L21/02661 , H01L29/1606 , H01L29/4908 , H01L29/513 , H01L29/66045 , H01L29/7781 , H01L29/78684
摘要： A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.
摘要翻译：在石墨烯层的最上表面上设置氮化硅层，然后在氮化硅层的最上表面上设置二氧化铪层。氮化硅层用作二氧化铪层的润湿剂，从而防止在石墨烯层顶上形成不连续的二氧化铪塔。共同形成低EOT双层栅极电介质的氮化硅层和二氧化铪层在石墨烯层的顶部呈现连续的形态。

58. 发明授权

US08455297B1 Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology 有权
标题翻译：通过三维集成技术制造高性能碳纳米管晶体管集成电路的方法
公开(公告)号：US08455297B1
公开(公告)日：2013-06-04
申请号：US12831656
申请日：2010-07-07
申请人： Phaedon Avouris , Kuan-Neng Chen , Yu-Ming Lin
发明人： Phaedon Avouris , Kuan-Neng Chen , Yu-Ming Lin
IPC分类号： H01L51/40
CPC分类号： H01L21/768 , B82Y10/00 , B82Y40/00 , H01L21/50 , H01L21/6835 , H01L21/76885 , H01L23/4827 , H01L2221/1094 , H01L2221/68359 , H01L2224/83894 , H01L2924/01025 , H01L2924/01029 , H01L2924/01046
摘要： Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.
摘要翻译：提供了制造基于碳纳米管的器件的技术。一方面，提供一种制造碳纳米管集成电路的方法。该方法包括以下步骤。提供了包括碳纳米管的第一晶片。提供包括一个或多个器件元件的第二晶片。一个或多个碳纳米管通过将第一晶片和第二晶片结合在一起而与一个或多个器件元件连接。还提供了一种基于碳纳米管的集成电路。

59. 发明授权

US08344358B2 Graphene transistor with a self-aligned gate 有权
标题翻译：具有自对准栅极的石墨烯晶体管
公开(公告)号：US08344358B2
公开(公告)日：2013-01-01
申请号：US12876454
申请日：2010-09-07
申请人： Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
发明人： Phaedon Avouris , Damon B. Farmer , Yu-Ming Lin , Yu Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/1606 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66742 , H01L29/778 , H01L29/78684
摘要： A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.
摘要翻译：基于石墨烯的场效应晶体管包括与栅电极自对准的源极和漏极。在图案化的石墨烯层上沉积种子层和电介质金属氧化物层的堆叠。第一金属部分和第二金属部分的导电材料堆叠形成在电介质金属氧化物层的上方。使用第二金属部分横向蚀刻第一金属部分，去除电介质金属氧化物层的暴露部分以形成其中第二金属部分悬垂在第一金属部分上的栅极结构。移除晶种层并且在定向沉积工艺期间使用突出部来遮蔽栅极结构周围的近端区域，以形成与栅电极的边缘自对准且最小程度地横向间隔的源电极和漏电极。

60. 发明申请

US20120326129A1 METAL-FREE INTEGRATED CIRCUITS COMPRISING GRAPHENE AND CARBON NANOTUBES 有权
标题翻译：包含石墨和碳纳米管的无金属集成电路
公开(公告)号：US20120326129A1
公开(公告)日：2012-12-27
申请号：US13604254
申请日：2012-09-05
申请人： Yu-Ming Lin , Jeng-Bang Yau
发明人： Yu-Ming Lin , Jeng-Bang Yau
IPC分类号： H01L29/78
CPC分类号： H01L29/1606 , B82Y10/00 , H01L27/124 , H01L29/0665 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78618 , H01L29/78684
摘要： An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.
摘要翻译：集成电路包括石墨烯层，所述石墨烯层包括未掺杂的石墨烯的区域，所述未掺杂的石墨烯包括晶体管的沟道和掺杂的石墨烯的区域，所述掺杂的石墨烯包括所述晶体管的接触; 和晶体管的栅极，所述栅极包括碳纳米管膜。一种制造包括石墨烯和碳纳米管的集成电路的方法，包括形成石墨烯层; 掺杂一部分石墨烯层，导致掺杂的石墨烯和未掺杂的石墨烯; 形成碳纳米管膜; 以及蚀刻所述碳纳米管膜以形成晶体管的栅极，其中所述晶体管还包括包含所述未掺杂的石墨烯的沟道和包含所述掺杂石墨烯的接触。晶体管包括栅极，栅极包括碳纳米管膜; 通道，通道包括未掺杂的石墨烯; 和触点，所述触点包括掺杂的石墨烯。

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