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51. 发明授权

US07111225B2 Viterbi bit detection method and device 失效
标题翻译：维特比比特检测方法及装置
公开(公告)号：US07111225B2
公开(公告)日：2006-09-19
申请号：US10528939
申请日：2003-08-13
申请人： Willem Marie Julia Marcel Coene , Albert Hendrik Jan Immink , Johannes Wilhelmus Maria Bergmans
发明人： Willem Marie Julia Marcel Coene , Albert Hendrik Jan Immink , Johannes Wilhelmus Maria Bergmans
IPC分类号： G03M13/03
CPC分类号： G11B20/1217 , G11B20/10009 , G11B20/10296 , G11B20/22 , G11B2020/1249 , G11B2020/1288 , G11B2220/2541
摘要： A Viterbi bit detection method for detecting the bit values of bits of a channel data stream stored on a record carrier along an N-dimensional channel tube, N being at least two, of at least two bit rows one-dimensionally evolving along a first direction and being aligned with each other along at least a second of N−1 other directions, the first direction together with the N−1 other directions constituting an N-dimensional lattice of bit positions, includes application of a row-based one-dimensional Viterbi bit detection method independent for each of the bit rows of said channel tube. To achieve a reliable bit detection, a number of independent one-dimensional row-based Viterbi bit detectors, also known as sequence detectors, is used, one for each bit row in the channel tube: the interference between successive neighboring bit rows is taken into account via the computation of the branch metrics (for the considered bit row), in which local bit decisions on the primary neighboring bits in the neighboring rows are used. As local bit detectors going beyond the performance of a threshold detector, the use of a HD-2 or HD-3-like hard-decision bit detector is proposed.
摘要翻译：一种维特比比特检测方法，用于检测沿N维通道管存储在记录载体上的信道数据流的比特值，N是沿着第一方向一维演化的至少两个比特行的至少两个并且沿着N-1个其他方向中的至少第二个方向彼此对准，第一方向与构成比特位置的N维格子的N-1个其他方向一起包括应用基于行的一维维特比位检测方法独立于所述通道管的每个位行。为了实现可靠的比特检测，使用了许多独立的一维行维特比比特检测器（也称为序列检测器），一个用于信道管中的每一比特行：连续相邻比特行之间的干扰被采用通过计算分支度量（对于考虑的比特行），其中使用相邻行中的主相邻比特的本地比特决定。随着本地位检测器超出门限检测器的性能，提出了使用HD-2或HD-3类硬判决位检测器。

52. 发明授权

US06762987B2 Slicer arrangement 失效
标题翻译：切片机布置
公开(公告)号：US06762987B2
公开(公告)日：2004-07-13
申请号：US09753742
申请日：2001-01-02
申请人： Gerardus Rudolph Langereis , Willem Marie Julia Marcel Coene , Constant Paul Marie Jozef Baggen , Johannus Leopoldus Bakx
发明人： Gerardus Rudolph Langereis , Willem Marie Julia Marcel Coene , Constant Paul Marie Jozef Baggen , Johannus Leopoldus Bakx
IPC分类号： G11B700
CPC分类号： G11B20/1403 , G11B7/00375 , G11B7/005 , G11B20/10009
摘要： A circuit arrangement including means for determining a slicer level from incoming signal levels for slicing the incoming signal levels on the basis of the slicer level thus determined, includes a first and a second register circuit, which register circuits are connected to an output of a discriminator circuit. The discriminator circuit compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit if the incoming signal level is higher than the set discrimination level and to apply and incoming signal level to the second register circuit if the incoming signal level is lower than the set termination level. The first and the second register circuit are adapted to determine a register value of a least two different incoming signal levels consecutively applied to the register circuit. The circuit supplies a signal having a level which is a value determine from register values determined by the first and second register circuit. The supplied signal represents both the set discrimination level and the slicer level.
摘要翻译：一种电路装置，包括用于根据输入信号电平确定限幅器电平的装置，用于基于如此确定的限幅器电平对输入信号电平进行限幅，包括第一和第二寄存器电路，该寄存器电路连接到鉴别器的输出端电路。鉴频器电路将输入信号电平与设定的鉴别电平进行比较，并且适于将输入信号电平施加到第一寄存器电路，如果输入信号电平高于设定的判别电平，并且将第二寄存器的输入信号电平施加到输入信号电平如果输入信号电平低于设定的终端电平。第一和第二寄存器电路适于确定连续施加到寄存器电路的至少两个不同输入信号电平的寄存器值。电路提供具有从由第一和第二寄存器电路确定的寄存器值确定的值的电平的信号。所提供的信号表示设定的辨别电平和限幅器电平。

53. 发明授权

US06678862B1 Detection apparatus 失效
标题翻译：检测装置
公开(公告)号：US06678862B1
公开(公告)日：2004-01-13
申请号：US09806585
申请日：2001-03-30
申请人： Johannes Wilhelmus Maria Bergmans , Willem Marie Julia Marcel Coene , Rob Otte , Simon Derek Bramwell
发明人： Johannes Wilhelmus Maria Bergmans , Willem Marie Julia Marcel Coene , Rob Otte , Simon Derek Bramwell
IPC分类号： H03M1303
CPC分类号： H03M13/6343 , G11B20/00 , H03M13/015 , H03M13/3961 , H03M13/41 , H03M13/4107 , H03M13/4169
摘要： A partial response maximum likelihood (PRML) bit detection apparatus is disclosed for deriving a bit sequence (xk) from an input information signal. The apparatus comprises input means for receiving the input information signal. The apparatus further comprises sampling means for sampling the input information signal at sampling instants so as to obtain samples (zk) of the information signal at said sampling instants. The apparatus also comprises calculating means (50, 70) for (a) calculating (50) at a sampling instant ti for one or more of a plurality of states sj (Sa, Sb, Sc) at said sampling instant, an optimum path metric value PM(sj,ti) and for determining for said one or more states a best predecessor state at the directly preceding sampling instant ti−1, a state at said sampling instant identifying a sequence of n subsequent bits. The apparatus further comprises calculating means for (b) establishing (70) the best path from the state at the said sampling instant ti having the lowest optimum path metric value, back in time towards the sampling instant ti−N via best predecessor states, established earlier for earlier sampling instants, to establish an optimum state at said sampling instant ti−N. The apparatus further comprises the calculating means for (c) outputting at least one bit (xk−MB−1) of said n bits of the sequence of bits corresponding to said established optimum state at said sampling instant ti−N. The steps (a) to (c) are repeated for a subsequent sampling instant ti+1. The apparatus is characterized in that mutually complementary sequences of n subsequent bits are allocated to the same state.
摘要翻译：公开了用于从输入信息信号导出比特序列（xk）的部分响应最大似然（PRML）比特检测装置。该装置包括用于接收输入信息信号的输入装置。该装置还包括用于在采样时刻对输入信息信号进行采样的采样装置，以便在所述采样时刻获得信息信号的采样（zk）。所述装置还包括计算装置（50,70），用于（a）在所述采样时刻的多个状态sj（Sa，Sb，Sc）中的一个或多个的采样时刻ti计算（50）最佳路径度量值PM（sj，ti），并且用于为所述一个或多个状态确定在直接在前的采样时刻ti-1处的最佳前置状态，所述采样时刻处的状态识别n个后续位的序列。该装置还包括计算装置，用于（b）建立（70）从具有最低最优路径度量值的所述采样时刻ti的状态建立（70）最佳路径，经过最佳前置状态向时间向采样时刻ti-N建立较早的采样时刻，以在所述采样时刻ti-N建立最佳状态。该装置还包括计算装置，用于（c）在所述采样时刻ti-N处输出与所述建立的最佳状态相对应的比特序列的所述n比特的至少一个比特（xk-MB-1）。对于随后的采样时刻ti + 1重复步骤（a）至（c）。该装置的特征在于将n个后续比特的互补序列分配给相同的状态。

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