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    • 1. 发明授权
    • Slicer arrangement
    • 切片机布置
    • US06762987B2
    • 2004-07-13
    • US09753742
    • 2001-01-02
    • Gerardus Rudolph LangereisWillem Marie Julia Marcel CoeneConstant Paul Marie Jozef BaggenJohannus Leopoldus Bakx
    • Gerardus Rudolph LangereisWillem Marie Julia Marcel CoeneConstant Paul Marie Jozef BaggenJohannus Leopoldus Bakx
    • G11B700
    • G11B20/1403G11B7/00375G11B7/005G11B20/10009
    • A circuit arrangement including means for determining a slicer level from incoming signal levels for slicing the incoming signal levels on the basis of the slicer level thus determined, includes a first and a second register circuit, which register circuits are connected to an output of a discriminator circuit. The discriminator circuit compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit if the incoming signal level is higher than the set discrimination level and to apply and incoming signal level to the second register circuit if the incoming signal level is lower than the set termination level. The first and the second register circuit are adapted to determine a register value of a least two different incoming signal levels consecutively applied to the register circuit. The circuit supplies a signal having a level which is a value determine from register values determined by the first and second register circuit. The supplied signal represents both the set discrimination level and the slicer level.
    • 一种电路装置,包括用于根据输入信号电平确定限幅器电平的装置,用于基于如此确定的限幅器电平对输入信号电平进行限幅,包括第一和第二寄存器电路,该寄存器电路连接到鉴别器的输出端 电路。 鉴频器电路将输入信号电平与设定的鉴别电平进行比较,并且适于将输入信号电平施加到第一寄存器电路,如果输入信号电平高于设定的判别电平,并且将第二寄存器的输入信号电平施加到输入信号电平 如果输入信号电平低于设定的终端电平。 第一和第二寄存器电路适于确定连续施加到寄存器电路的至少两个不同输入信号电平的寄存器值。 电路提供具有从由第一和第二寄存器电路确定的寄存器值确定的值的电平的信号。 所提供的信号表示设定的辨别电平和限幅器电平。
    • 2. 发明授权
    • Method of storing or decoding a stream of bits
    • 存储或解码比特流的方法
    • US07174497B2
    • 2007-02-06
    • US09933791
    • 2001-08-21
    • Constant Paul Marie Jozef BaggenMarten Erik Van DijkWillem Marie Julia Marcel Coene
    • Constant Paul Marie Jozef BaggenMarten Erik Van DijkWillem Marie Julia Marcel Coene
    • H03M13/00
    • H03M13/27G11B20/1426H03M5/14H03M5/145H03M13/1515
    • The invention relates to a method of storing a number of data bits of a secondary channel (30) in the frame of a main channel (20) and to a method of decoding a stream of bits relating to a secondary channel (30) embedded in the frames of a main channel (20) into a stream of data bits (62). In order to enable a certain synchronization and to guarantee a fixed amount of storage capacity in the secondary channel as well as to be able to correct deletions or insertions of bits in the secondary channel it is proposed according to the invention to form a secondary frame (11) having a fixed number of frame bits, to fill a fixed part of the secondary frame (11) with data bits (113), an end-bit (114) set to a first bit-value and, if necessary, with filling bits (115) set to a second bit-value, to encode the secondary frame (11) producing encoded data bits (113) and parity bits (112), which are finally embedded in the frame of the main channel (20). The invention relates also to a device for storing a number of data bits of the secondary channel (30) in the frame of a main channel (20) and to a device for decoding a stream of bits of relating to a secondary channel (30) embedded in the frames of a main channel (20).
    • 本发明涉及一种在主信道(20)的帧中存储辅助信道(30)的多个数据位的方法,以及一种解码与嵌入在第二信道(30)中的辅助信道(30)有关的位流的方法 主通道(20)的帧转换成数据位流(62)。 为了实现一定的同步并且保证次级信道中的固定量的存储容量以及能够纠正次级信道中的位的删除或插入,根据本发明提出了形成辅助帧( 11)具有固定数量的帧比特,以数据比特(113)填充辅助帧(11)的固定部分,将终端位(114)设置为第一比特值,并且如果需要,填充 位(115)被设置为第二位值,以编码产生编码数据位(113)和奇偶校验位(112)的辅助帧(11),其最终嵌入在主通道(20)的帧中。 本发明还涉及一种用于在主信道(20)的帧中存储辅助信道(30)的多个数据比特的装置和用于解码与次信道(30)有关的比特流的装置, 嵌入在主通道(20)的框架中。
    • 4. 发明申请
    • Coder and a Method of Coding For Codes With a Parity-Complementary Word Assignment Having a Constraint of D1=,R=2
    • 编码器和编码代码的方法,其中具有约束D1 =,R = 2的奇偶互补字分配
    • US20090015446A1
    • 2009-01-15
    • US12097570
    • 2006-12-08
    • Willem Marie Julia Marcel CoeneAndries Pieter HekstraHiroyuki YamagishiMakoto Noda
    • Willem Marie Julia Marcel CoeneAndries Pieter HekstraHiroyuki YamagishiMakoto Noda
    • H03M7/00
    • G11B20/1426G11B20/10055G11B20/10296G11B2020/1453G11B2020/1457H03M5/145H03M7/40H03M13/29H03M13/31H03M13/3761H03M13/3972H03M13/41
    • Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t. In the code according to the invention the overall code has the property that the respective channel bit sequences that are encoded from the same message-bit sequence, starting from any possible state of the finite-state-machine, for each of the two values of a DC-control bit, that is part of a given user word have opposite parities for the sequences generated from the starting state up to the state where both encoder paths merge. For the case that the encoder paths do not merge, there is no such constraint. Finally, a new d=1, k=10 sliding-block decodable RLL code is disclosed with the following properties: (i) it has an r=2 constraint which is the lowest MTR value that is compatible with a rate R=⅔; (ii) it enables practical SISO-RLL decoding because of its compact 2-to-3 mapping; and (iii) the new code uses a parity-complementary word assignment4 (PCWA) for DC-control.
    • 目前已知的d = 1代码具有由连续的2T运行组成的长列,并且总体出现最短的2T运行的频率,从而降低位检测器的性能通过使用MTR约束为2的代码,改进了位检测 已完成。 提出了一种以系统方式构建的代码,其提供MTR约束为2的代码。 公开了这样的代码的变型,其中使用一个子代码,其中编码状态被分为编码类别以及代码字被分成代码字类型。 然后,对于给定子码,如果所述下一子码的所述后续码字属于编码类的编码状态之一,则可以将类型t的码字与下一子码的码字连接, 指数Tmax + 1t。 在根据本发明的代码中,总代码具有以下特性:从相同消息比特序列编码的各个信道比特序列,从有限状态机的任何可能状态开始,对于两个值的 作为给定用户字的一部分的DC控制位对于从起始状态直到两个编码器路径合并的状态产生的序列具有相反的奇偶校验。 对于编码器路径不合并的情况,没有这样的限制。 最后,公开了一种新的d = 1,k = 10滑块可解码的RLL码,具有以下特性:(i)它具有r = 2约束,其是与速率R = 2 / 3; (ii)由于其紧凑的2对3映射,它使实用的SISO-RLL解码成为可能; 和(iii)新的代码使用奇偶互补字分配4(PCWA)进行DC控制。
    • 6. 发明授权
    • Coder and a method of coding for codes having a Repeated Maximum Transition Run constraint of 2
    • 编码器和编码具有重复最大转换运行约束的代码的方法2
    • US07403138B2
    • 2008-07-22
    • US11575079
    • 2005-09-08
    • Willem Marie Julia Marcel Coene
    • Willem Marie Julia Marcel Coene
    • H03M5/00
    • G11B20/1426G11B2020/1453H03M5/145
    • Presently known codes have long trains consisting of 2T runs that reduce the performance of the bit detector. By using a code with an RMTR constraint of 2 an improvement in the bit detection is achieved. A code constructed is a systematic way that provides an RMTR constraint of 2 is presented. Several variations of such a code are disclosed where one or more sub-codes are used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, a code word type t can be concatenated with a code word of the next sub-code if the subsequent code word of the next sub-code belongs to one of coding states of the coding class with index Tmax+1−t.
    • 目前已知的代码具有由2T运行组成的长列车,降低了位检测器的性能。 通过使用RMTR约束为2的代码,实现了位检测的改进。 构建的代码是提供RMTR约束为2的系统方法。 公开了这样的代码的几个变型,其中使用一个或多个子代码,其中编码状态被分为编码类别以及代码字被划分为代码字类型。 然后,对于给定的子代码,如果下一子代码的后续代码字属于具有索引的编码类的编码状态之一,则代码字类型t可以与下一子代码的代码字连接 最大+ 1-t。