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51. 发明授权

US08895447B2 Semiconductor hole structure 有权
标题翻译：半导体孔结构
公开(公告)号：US08895447B2
公开(公告)日：2014-11-25
申请号：US13608794
申请日：2012-09-10
申请人： Nien-Yu Tsai , Wei Ming Chen
发明人： Nien-Yu Tsai , Wei Ming Chen
IPC分类号： H01L21/311
CPC分类号： H01L21/76831 , H01L21/02063 , H01L21/31144 , H01L21/76805 , H01L21/76814
摘要： A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.
摘要翻译：第一电介质层形成在衬底上。在第一电介质层上形成第二电介质层。在第二电介质层中形成第一开口。在第一介电层中形成第二开口。

52. 发明授权

US08723316B2 Chip package structure using flexible substrate 有权
标题翻译：芯片封装结构采用柔性基板
公开(公告)号：US08723316B2
公开(公告)日：2014-05-13
申请号：US13481881
申请日：2012-05-28
申请人： Wei-Ming Chen , Chi-Chia Huang
发明人： Wei-Ming Chen , Chi-Chia Huang
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/4985 , H01L21/563 , H01L23/49894 , H01L23/552 , H01L23/60 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/26175 , H01L2224/32225 , H01L2224/73204 , H01L2224/81203 , H01L2224/81805 , H01L2924/00014 , H01L2924/01322 , H01L2924/3511 , H01L2924/00 , H01L2224/0401
摘要： A chip package structure includes a flexible substrate having a chip mounting region, a plurality of leads disposed on the flexible substrate, an insulating layer and a chip. Each lead includes a body portion and an inner lead portion connected to each other. The body portion is located outside the chip mounting region and has a thickness greater than that of the inner lead portion. The insulating layer is disposed on the inner lead portions. The chip has an active surface on which a plurality of bumps and a seal ring adjacent to the chip edges are disposed. The chip is mounted within the chip mounting region and electrically connects the flexible substrate by connecting the inner lead portions of the leads with the bumps. The insulating layer is corresponding to the seal ring in position when the chip is electrically connected to the flexible substrate.
摘要翻译：芯片封装结构包括具有芯片安装区域的柔性衬底，设置在柔性衬底上的多个引线，绝缘层和芯片。每个引线包括彼此连接的主体部分和内部引线部分。主体部分位于芯片安装区域的外侧，其厚度大于内部引线部分的厚度。绝缘层设置在内引线部分上。芯片具有活性表面，多个凸起和与芯片边缘相邻的密封环设置在该表面上。芯片安装在芯片安装区域内，通过将引线的内引线部分与凸块连接来电连接柔性基板。当芯片电连接到柔性基板时，绝缘层对应于密封环就位。

53. 发明授权

US08410599B2 Power MOSFET package 有权
标题翻译：功率MOSFET封装
公开(公告)号：US08410599B2
公开(公告)日：2013-04-02
申请号：US12756915
申请日：2010-04-08
申请人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
发明人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
IPC分类号： H01L23/04
CPC分类号： H01L29/78 , H01L23/3114 , H01L23/481 , H01L23/492 , H01L24/13 , H01L24/16 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/7802 , H01L29/7809 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/01021 , H01L2924/13091 , H01L2224/05599 , H01L2224/05099
摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.
摘要翻译：功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二，并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

54. 发明申请

US20120192932A1 SOLAR CELL AND ITS ELECTRODE STRUCTURE 审中-公开
标题翻译：太阳电池及其电极结构
公开(公告)号：US20120192932A1
公开(公告)日：2012-08-02
申请号：US13441867
申请日：2012-04-07
申请人： MENG-HSIU WU , YU-WEI TAI , WEI-MING CHEN , YANG-FANG CHEN
发明人： MENG-HSIU WU , YU-WEI TAI , WEI-MING CHEN , YANG-FANG CHEN
IPC分类号： H01L31/0224
CPC分类号： H01L31/022425 , H01L31/022433 , Y02E10/50
摘要： An electrode structure is disposed on a substrate of a solar cell. The electrode structure includes a plurality of bus electrodes, a plurality of finger electrodes, and at least one connection electrode. The bus electrodes are separately disposed on the substrate. The finger electrodes are disposed on two sides of the bus electrodes and electrically connect to the bus electrodes. The connection electrode is disposed on a side of the substrate and connects with at least two finger electrodes. The connection electrode, bus electrodes and the finger electrodes are formed by at least two screen printing processes, and at least one of the screen printing processes does not form the bus electrodes. Thus, the thicknesses of the finger electrodes are greater than those of the bus electrodes.
摘要翻译：电极结构设置在太阳能电池的基板上。电极结构包括多个总线电极，多个指状电极和至少一个连接电极。总线电极分别设置在基板上。手指电极设置在总线电极的两侧，并且电连接到总线电极。连接电极设置在基板的一侧并与至少两个指状电极连接。连接电极，总线电极和指状电极通过至少两个丝网印刷工艺形成，并且丝网印刷工艺中的至少一个不形成总线电极。因此，指状电极的厚度大于总线电极的厚度。

55. 发明授权

US08227927B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08227927B2
公开(公告)日：2012-07-24
申请号：US12900190
申请日：2010-10-07
申请人： Wei-Ming Chen , Shu-Ming Chang
发明人： Wei-Ming Chen , Shu-Ming Chang
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L21/561 , H01L23/13 , H01L23/5389 , H01L24/13 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2223/5442 , H01L2223/54426 , H01L2224/12105 , H01L2224/13022 , H01L2224/24051 , H01L2224/24101 , H01L2224/24105 , H01L2224/24137 , H01L2224/24146 , H01L2224/24226 , H01L2224/244 , H01L2224/245 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/821 , H01L2224/8313 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83851 , H01L2224/92244 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , Y10S438/975 , H01L2924/00014 , H01L2924/00 , H01L2224/83 , H01L2924/00012
摘要： A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.
摘要翻译：公开了一种芯片封装。该封装包括载体衬底和其上至少两个半导体芯片。每个半导体芯片包括多个导电焊盘。位置结构设置在载体基板上以将半导体芯片的位置固定在载体基板上。填充材料层形成在载体基板上，覆盖半导体芯片和位置结构，并且具有多个对应地暴露导电焊盘的开口。再分配层（RDL）设置在填充材料层上并且通过多个开口连接到导电焊盘。保护层覆盖填充材料层和RDL。多个导电凸块设置在保护层上并与RDL电连接。还公开了芯片封装的制造方法。

56. 发明申请

US20110193225A1 ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US20110193225A1
公开(公告)日：2011-08-11
申请号：US13024902
申请日：2011-02-10
申请人： Wei-Ming CHEN , Shu-Ming CHANG
发明人： Wei-Ming CHEN , Shu-Ming CHANG
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/49811 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/82 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2224/24246 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/82 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/00 , H01L2224/83
摘要： A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.
摘要翻译：公开了一种芯片封装。封装包括载体衬底，至少两个半导体芯片，填充材料层，保护层和多个导电凸块。载体基板包括接地区域。半导体芯片设置在载体基板的接地区域上。每个半导体芯片包括至少一个信号焊盘，并且包括电连接到接地区域的至少一个接地焊盘。填充材料层形成在载体衬底上并覆盖半导体芯片。保护层覆盖填充层。多个导电凸块设置在保护层的上方并与半导体芯片电连接。还公开了芯片封装的制造方法。

57. 发明申请

US20110152429A1 Composition and Process for Preparing NIR Shielding Masterbatch and NIR Shielding Masterbatch and Application Thereof 有权
标题翻译：制备NIR屏蔽母粒和NIR屏蔽母粒及其应用的组成和工艺
公开(公告)号：US20110152429A1
公开(公告)日：2011-06-23
申请号：US12851583
申请日：2010-08-06
申请人： Ying-Hsiu Hsiao , Sheng-Jen Lin , Wei-Ming Chen , Wei-Peng Lin
发明人： Ying-Hsiu Hsiao , Sheng-Jen Lin , Wei-Ming Chen , Wei-Peng Lin
IPC分类号： C08K3/22 , C08L67/00 , C08L77/00 , C08L23/12 , C08K3/30
CPC分类号： G02B1/04 , C08J5/00 , D01F1/106
摘要： Disclosed herein is a method for preparing a near infrared shielding masterbatch. The method includes the steps of preparing and compounding a composition, and then pelletizing the compounded composition. The composition includes at least one metallic ionic compound powder in an amount of about 1-25 wt %, a cross-linking agent in an amount of about 0.1-5 wt %, a thermoplastic polymer in an amount of about 67-98.7 wt %, an initiator in an amount of about 0.1-1 wt %, and a dispersing agent in an amount of about 0.1-2 wt %.
摘要翻译：本文公开了一种制备近红外屏蔽母料的方法。该方法包括制备和混合组合物，然后将复合组合物造粒的步骤。该组合物包含至少一种量为约1-25重量％的金属离子化合物粉末，约0.1-5重量％的交联剂，约67-98.7重量％的热塑性聚合物，，约0.1-1重量％的引发剂和约0.1-2重量％的分散剂。

58. 发明申请

US20110098391A1 Non-Dripping Flame Retarding Masterbatch , Composition and Process for Preparing the Same and Flame Retarding Article Containing the Same 有权
标题翻译：非滴漏阻燃母料，其制备方法及其制备方法及其阻燃物品
公开(公告)号：US20110098391A1
公开(公告)日：2011-04-28
申请号：US12648083
申请日：2009-12-28
申请人： Sheng-Jen Lin , Wei-Ming Chen , Nai-Yun Liang , Wei-Peng Lin
发明人： Sheng-Jen Lin , Wei-Ming Chen , Nai-Yun Liang , Wei-Peng Lin
IPC分类号： C08K5/09 , C08K3/32 , C08K5/10 , C08L67/00 , C08L77/00 , C08L23/12 , C08L27/06 , C08L67/02
CPC分类号： C08K5/0025 , C08J3/226 , C08J2427/00 , C08J2467/00 , C08J2477/00 , C08K3/32 , C08K5/0066 , C08L23/12 , C08L23/10 , C08L67/02 , C08L27/06 , C08L77/00 , C08L2666/02
摘要： Disclosed herein is a composition for preparing a non-dripping flame retarding masterbatch. The flame retarding masterbatch includes a fire retardant in an amount of about 0.1-15.0 wt %, a crosslinking agent in an amount of about 0.1-1.5 wt %, a thermoplastic polymer in an amount of about 76.5-99.5 wt %, a crosslinking initiator in an amount of about 0.01-2.0 wt %, and a dispersing agent in an amount of about 0.1-5.0 wt % in the composition.
摘要翻译：本文公开了一种用于制备不滴加阻燃母料的组合物。阻燃母料包括约0.1-15.0重量％的阻燃剂，约0.1-1.5重量％的交联剂，约76.5-99.5重量％的热塑性聚合物，交联引发剂的量为约0.01-2.0重量％，分散剂的量为组合物中约0.1-5.0重量％。

59. 发明申请

US20110084382A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20110084382A1
公开(公告)日：2011-04-14
申请号：US12900190
申请日：2010-10-07
申请人： Wei-Ming Chen , Shu-Ming Chang
发明人： Wei-Ming Chen , Shu-Ming Chang
IPC分类号： H01L23/498 , H01L21/56
CPC分类号： H01L23/544 , H01L21/561 , H01L23/13 , H01L23/5389 , H01L24/13 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/83 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2223/5442 , H01L2223/54426 , H01L2224/12105 , H01L2224/13022 , H01L2224/24051 , H01L2224/24101 , H01L2224/24105 , H01L2224/24137 , H01L2224/24146 , H01L2224/24226 , H01L2224/244 , H01L2224/245 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/821 , H01L2224/8313 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83851 , H01L2224/92244 , H01L2224/97 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , Y10S438/975 , H01L2924/00014 , H01L2924/00 , H01L2224/83 , H01L2924/00012
摘要： A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed.
摘要翻译：公开了一种芯片封装。该封装包括载体衬底和其上至少两个半导体芯片。每个半导体芯片包括多个导电焊盘。位置结构设置在载体基板上以将半导体芯片的位置固定在载体基板上。填充材料层形成在载体基板上，覆盖半导体芯片和位置结构，并且具有多个对应地暴露导电焊盘的开口。再分配层（RDL）设置在填充材料层上并且通过多个开口连接到导电焊盘。保护层覆盖填充材料层和RDL。多个导电凸块设置在保护层上并与RDL电连接。还公开了芯片封装的制造方法。

60. 发明授权

US07663237B2 Butted contact structure 失效
标题翻译：对接接触结构
公开(公告)号：US07663237B2
公开(公告)日：2010-02-16
申请号：US11320512
申请日：2005-12-27
申请人： Yuan-Ching Peng , Chloe Hsin-yi Chen , David Hsu-Wei Lwu , Shyue-Shyh Lin , Wei-Ming Chen
发明人： Yuan-Ching Peng , Chloe Hsin-yi Chen , David Hsu-Wei Lwu , Shyue-Shyh Lin , Wei-Ming Chen
IPC分类号： H01L23/48
CPC分类号： H01L27/11 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L21/823481 , H01L27/1104 , H01L29/495 , H01L29/66545 , H01L29/7833
摘要： A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.
摘要翻译：提供半导体结构及其使用替代栅极工艺的方法。半导体结构包括耦合第一晶体管和栅极延伸的源极/漏极区域或源极/漏极区域上的硅化物的对接触点。半导体结构还包括在第一晶体管的源极/漏极区域上的电连接到源极/漏极区域的接触焊盘。接触焊盘的添加减小了接触电阻以及在对接触点和源极/漏极区域之间形成开路的可能性。接触垫优选地具有基本上与门延伸部的顶表面平齐的顶表面。

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