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1. 发明授权

US08410599B2 Power MOSFET package 有权
标题翻译：功率MOSFET封装
公开(公告)号：US08410599B2
公开(公告)日：2013-04-02
申请号：US12756915
申请日：2010-04-08
申请人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
发明人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
IPC分类号： H01L23/04
CPC分类号： H01L29/78 , H01L23/3114 , H01L23/481 , H01L23/492 , H01L24/13 , H01L24/16 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/7802 , H01L29/7809 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/01021 , H01L2924/13091 , H01L2224/05599 , H01L2224/05099
摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.
摘要翻译：功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二，并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

2. 发明申请

US20100289092A1 POWER MOSFET PACKAGE 有权
标题翻译：功率MOSFET封装
公开(公告)号：US20100289092A1
公开(公告)日：2010-11-18
申请号：US12756915
申请日：2010-04-08
申请人： Baw-Ching PERNG , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
发明人： Baw-Ching PERNG , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
IPC分类号： H01L29/78 , H01L23/538
CPC分类号： H01L29/78 , H01L23/3114 , H01L23/481 , H01L23/492 , H01L24/13 , H01L24/16 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/7802 , H01L29/7809 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/01021 , H01L2924/13091 , H01L2224/05599 , H01L2224/05099
摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.
摘要翻译：功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二，并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

3. 发明申请

US20110140267A1 ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电子设备包装及其制造方法
公开(公告)号：US20110140267A1
公开(公告)日：2011-06-16
申请号：US12849089
申请日：2010-08-03
申请人： Chia-Lun TSAI , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
发明人： Chia-Lun TSAI , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/20 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32225 , H01L2224/73267 , H01L2224/83132 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15184 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
摘要翻译：本发明提供一种电子器件封装及其制造方法。电子器件封装包括载体晶片。具有多个导电焊盘的电子器件芯片设置在载体晶片上。隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。隔离层压层具有多个开口以露出导电垫。在隔离层压层和开口中顺应地形成多个再分配图案。再分布图案分别电连接到导电焊盘。多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

4. 发明授权

US08541877B2 Electronic device package and method for fabricating the same 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US08541877B2
公开(公告)日：2013-09-24
申请号：US12849089
申请日：2010-08-03
申请人： Chia-Lun Tsai , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
发明人： Chia-Lun Tsai , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
IPC分类号： H01L23/48
CPC分类号： H01L24/20 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32225 , H01L2224/73267 , H01L2224/83132 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15184 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
摘要翻译：本发明提供一种电子器件封装及其制造方法。电子器件封装包括载体晶片。具有多个导电焊盘的电子器件芯片设置在载体晶片上。隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。隔离层压层具有多个开口以露出导电垫。在隔离层压层和开口中顺应地形成多个再分配图案。再分布图案分别电连接到导电焊盘。多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

5. 发明申请

US20110079892A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：芯片包装及其制造方法
公开(公告)号：US20110079892A1
公开(公告)日：2011-04-07
申请号：US12896277
申请日：2010-10-01
申请人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
发明人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L21/78 , H01L21/76898 , H01L23/552 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/92 , H01L24/94 , H01L2224/023 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13024 , H01L2224/2919 , H01L2224/73253 , H01L2224/9202 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2224/03 , H01L2224/11 , H01L2224/83 , H01L2924/0665 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
摘要翻译：芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

6. 发明授权

US08637970B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08637970B2
公开(公告)日：2014-01-28
申请号：US12855447
申请日：2010-08-12
申请人： Chia-Lun Tsai , Chia-Ming Cheng , Long-Sheng Yeou
发明人： Chia-Lun Tsai , Chia-Ming Cheng , Long-Sheng Yeou
IPC分类号： H01L21/301 , H01L21/302
CPC分类号： H01L21/78 , B81B2207/07 , B81B2207/098 , B81C1/00825 , B81C2201/014 , B81C2201/053 , B81C2203/0118
摘要： An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.
摘要翻译：本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层，形成随后的半导体制造工艺的开口。

7. 发明授权

US08399963B2 Chip package and fabrication method thereof 有权
标题翻译：芯片封装及其制造方法
公开(公告)号：US08399963B2
公开(公告)日：2013-03-19
申请号：US12896277
申请日：2010-10-01
申请人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
发明人： Chia-Lun Tsai , Tsang-Yu Liu , Chia-Ming Cheng
IPC分类号： H01L23/544 , H01L23/48
CPC分类号： H01L21/78 , H01L21/76898 , H01L23/552 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/92 , H01L24/94 , H01L2224/023 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13024 , H01L2224/2919 , H01L2224/73253 , H01L2224/9202 , H01L2224/94 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2224/03 , H01L2224/11 , H01L2224/83 , H01L2924/0665 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes a substrate having a pad region, a device region, and a remained scribe region located at a periphery of the substrate; a signal and an EMI ground pads disposed on the pad region; a first and a second openings penetrating into the substrate to expose the signal and the EMI ground pads, respectively; a first and a second conducting layers located in the first and the second openings and electrically connecting the signal and the EMI ground pads, respectively, wherein the first conducting layer and the signal pad are separated from a periphery of the remained scribe region, and wherein a portion of the second conducting layer and/or the EMI ground pad extend(s) to a periphery of the remained scribe region; and a third conducting layer surrounding the periphery of the remained scribe region to electrically connect the second conducting layer and/or the EMI ground pad.
摘要翻译：芯片封装包括具有焊盘区域，器件区域和位于衬底周围的残留刻划区域的衬底; 设置在所述焊盘区域上的信号和EMI接地焊盘; 分别穿入基板以暴露信号和EMI接地焊盘的第一和第二开口; 位于所述第一和第二开口中的第一和第二导电层，分别电连接所述信号和所述EMI接地焊盘，其中所述第一导电层和所述信号焊盘与所述残留划线区域的外围分离，并且其中所述第二导电层和/或所述EMI接地垫的一部分延伸到所述残留划线区域的周边; 以及围绕剩余划线区域的周边的第三导电层，以电连接第二导电层和/或EMI接地垫。

8. 发明申请

US20110127681A1 CHIP PACKAGE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：芯片包装及其制造方法
公开(公告)号：US20110127681A1
公开(公告)日：2011-06-02
申请号：US12958329
申请日：2010-12-01
申请人： Ching-Yu NI , Chia-Ming Cheng , Nan-Chun Lin
发明人： Ching-Yu NI , Chia-Ming Cheng , Nan-Chun Lin
IPC分类号： H01L23/485 , H01L21/60
CPC分类号： H01L23/498 , H01L21/78 , H01L23/3114 , H01L23/3192 , H01L24/06 , H01L2224/05624 , H01L2224/05647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/16195 , H01L2924/16235 , H01L2924/00014 , H01L2924/00
摘要： A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.
摘要翻译：根据本发明的实施例提供了芯片封装及其制造方法。芯片封装包括含有芯片并具有器件面积和外围焊盘区域的半导体衬底。多个导电焊盘设置在外围接合焊盘区域处，并且钝化层形成在半导体衬底上以露出导电焊盘。在器件区域的钝化层上形成绝缘保护层。封装层设置在绝缘保护层上方以在外围接合焊盘区域露出导电焊盘和钝化层。该方法包括在切割过程中形成绝缘保护层以覆盖多个导电焊盘，并且通过封装层的开口去除导电焊盘上的绝缘保护层。

9. 发明授权

US08384174B2 Chip package 有权
标题翻译：芯片封装
公开(公告)号：US08384174B2
公开(公告)日：2013-02-26
申请号：US13070375
申请日：2011-03-23
申请人： Hsin-Chih Chiu , Chia-Ming Cheng , Chuan-Jin Shiu , Bai-Yao Lou
发明人： Hsin-Chih Chiu , Chia-Ming Cheng , Chuan-Jin Shiu , Bai-Yao Lou
IPC分类号： H01L31/0203
CPC分类号： H01L31/02164 , H01L27/14618 , H01L33/486 , H01L33/54 , H01L33/62 , H01L2224/13
摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.
摘要翻译：芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离开口从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。

10. 发明申请

US20110233770A1 CHIP PACKAGE 有权
标题翻译：芯片包装
公开(公告)号：US20110233770A1
公开(公告)日：2011-09-29
申请号：US13070375
申请日：2011-03-23
申请人： Hsin-Chih CHIU , Chia-Ming Cheng , Chuan-Jin Shiu , Bai-Yao Lou
发明人： Hsin-Chih CHIU , Chia-Ming Cheng , Chuan-Jin Shiu , Bai-Yao Lou
IPC分类号： H01L23/498
CPC分类号： H01L31/02164 , H01L27/14618 , H01L33/486 , H01L33/54 , H01L33/62 , H01L2224/13
摘要： A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump.
摘要翻译：芯片封装包括：具有第一和第二表面的衬底; 第一表面上的光学装置; 第二表面上的导电层; 所述第二表面上的钝化层和所述导电层，其中所述钝化层具有暴露所述导电层的开口; 在第二表面上具有导电凸起并具有底部和上部，其中底部设置在开口中并与导电层电接触，并且上部位于开口的外侧，并沿远离开口从所述导电凸块的表面延伸到所述导电凸块的内部的凹部; 以及在所述第二表面上的遮光层，在所述上部下方延伸，并且部分地位于所述凹部中并与所述导电凸块的一部分重叠。

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