专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08298904B2 Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture 有权
标题翻译：紧凑的热控薄膜电阻器，利用基板触点和制造方法
公开(公告)号：US08298904B2
公开(公告)日：2012-10-30
申请号：US13008465
申请日：2011-01-18
申请人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
发明人： Joseph M. Lukaitis , Jed H. Rankin , Robert R. Robison , Dustin K. Slisher , Timothy D. Sullivan
IPC分类号： H01L21/20
CPC分类号： H01L27/1203 , H01L28/20
摘要： A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.
摘要翻译：形成半导体结构的方法包括在衬底上的绝缘体层上形成电阻器，并且在电阻器上方形成至少一个电介质层。所述方法还包括通过所述至少一个电介质层，通过所述电阻器，穿过所述绝缘体层，并进入所述衬底形成衬底接触。衬底接触包括高导热性材料。

52. 发明授权

US08232177B2 Method of generating uniformly aligned well and isolation regions in a substrate and resulting structure 有权
标题翻译：在衬底中产生均匀排列的阱和隔离区域以及所得结构的方法
公开(公告)号：US08232177B2
公开(公告)日：2012-07-31
申请号：US12570415
申请日：2009-09-30
申请人： Wagdi Abadeer , Lilian Kamal, legal representative , Kiran V Chatty , Robert J Gauthier, Jr. , Jed H Rankin , Robert R Robison , William Tonti
发明人： Wagdi Abadeer , Kiran V Chatty , Robert J Gauthier, Jr. , Jed H Rankin , Robert R Robison , William Tonti
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

53. 发明申请

US20120074501A1 USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
标题翻译：使用联系人创建设备上的差别应力
公开(公告)号：US20120074501A1
公开(公告)日：2012-03-29
申请号：US12892465
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/76879 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L27/092
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片，与PFET的源极/漏极区域的PFET接触以及与源极/漏极区域的NFET接触的NFET。在第一实施例中，在PFET接触和PFET的源极/漏极区之间仅包含PFET接触下的硅锗（SiGe）层。在第二实施例中，PFET触点延伸到PFET的源极/漏极区域中，或者NFET触点延伸到NFET的源极/漏极区域。

54. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

55. 发明申请

US20120018806A1 SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE WITH SELECTIVELY PLACED SUB-INSULATOR LAYER VOID(S) AND METHOD OF FORMING THE SOI STRUCTURE 有权
标题翻译：具有选择性的绝缘子层绝缘体的半导体绝缘体（SOI）结构和形成SOI结构的方法
公开(公告)号：US20120018806A1
公开(公告)日：2012-01-26
申请号：US12842146
申请日：2010-07-23
申请人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
发明人： Toshiharu Furukawa , Robert R. Robison , Richard Q. Williams
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/66477 , H01L21/02104 , H01L21/84 , H01L27/1203 , H01L29/78648 , H01L29/78654
摘要： Disclosed is a semiconductor-on-insulator (SOI) structure having sub-insulator layer void(s) selectively placed in a substrate so that capacitance coupling between a first section of a semiconductor layer and the substrate will be less than capacitance coupling between a second section of the semiconductor layer and the substrate. The first section may contain a first device on an insulator layer and the second section may contain a second device on the insulator layer. Alternatively, the first and second sections may comprise different regions of the same device on an insulator layer. For example, in an SOI field effect transistor (FET), sub-insulator layer voids can be selectively placed in the substrate below the source, drain and/or body contact diffusion regions, but not below the channel region so that capacitance coupling between the these various diffusion regions and the substrate will be less than capacitance coupling between the channel region and the substrate. Also, disclosed is an associated method of forming such an SOI structure.
摘要翻译：公开了一种绝缘体半导体（SOI）结构，其具有选择性地放置在衬底中的次绝缘体层空穴，使得半导体层的第一部分与衬底之间的电容耦合将小于第二半导体层和衬底的截面。第一部分可以包含绝缘体层上的第一器件，第二部分可以在绝缘体层上包含第二器件。或者，第一和第二部分可以包括绝缘体层上相同器件的不同区域。例如，在SOI场效应晶体管（FET）中，可以将子绝缘体层空隙选择性地放置在源极，漏极和/或体接触扩散区域下方的衬底中，但不能在沟道区域下方，使得电容耦合这些各种扩散区域和衬底将小于沟道区域和衬底之间的电容耦合。此外，公开了形成这种SOI结构的相关方法。

56. 发明授权

US07936017B2 Reduced floating body effect without impact on performance-enhancing stress 有权
标题翻译：降低浮体效应，而不影响性能增强应力
公开(公告)号：US07936017B2
公开(公告)日：2011-05-03
申请号：US12120836
申请日：2008-05-15
申请人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
发明人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/66772 , H01L29/7848 , H01L29/78612 , H01L29/78621
摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.
摘要翻译：提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

57. 发明申请

US20110095393A1 CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS 有权
标题翻译：创造出具有重大均匀厚度的极细半导体绝缘体（ETSOI）
公开(公告)号：US20110095393A1
公开(公告)日：2011-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06 , H01L21/66 , C23F1/08
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

58. 发明申请

US20110079827A1 STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION 有权
标题翻译：在金属栅沉积期间产生大气局部互连的结构和方法
公开(公告)号：US20110079827A1
公开(公告)日：2011-04-07
申请号：US12573188
申请日：2009-10-05
申请人： John J. ELLIS-MONAGHAN , Jeffrey P. GAMBINO , Kirk D. PETERSON , Jed H. RANKIN , Robert R. ROBISON
发明人： John J. ELLIS-MONAGHAN , Jeffrey P. GAMBINO , Kirk D. PETERSON , Jed H. RANKIN , Robert R. ROBISON
IPC分类号： H01L29/78 , H01L21/28 , H01L21/768 , H01L23/48
CPC分类号： H01L21/76895 , H01L21/76816 , H01L27/1248 , H01L29/517 , H01L29/66545
摘要： A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.
摘要翻译：在金属栅极沉积期间创建镶嵌局部互连的方法和结构。一种方法包括：在衬底的上表面上形成栅电介质; 在栅极电介质上形成心轴; 在与心轴相同的水平上形成层间电介质（ILD）层; 在ILD层中形成沟槽; 去除心轴; 以及在栅极电介质和沟槽中形成金属层。

59. 发明申请

US20110073985A1 Method of Generating Uniformly Aligned Well and Isolation Regions in a Substrate and Resulting Structure 有权
标题翻译：在基板和结构中产生均匀排列的井和隔离区域的方法
公开(公告)号：US20110073985A1
公开(公告)日：2011-03-31
申请号：US12570415
申请日：2009-09-30
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
IPC分类号： H01L29/06 , H01L23/00 , H01L21/762
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

60. 发明授权

US07790564B2 Methods for fabricating active devices on a semiconductor-on-insulator substrate utilizing multiple depth shallow trench isolations 失效
标题翻译：使用多深度浅沟槽隔离件在绝缘体上半导体衬底上制造有源器件的方法
公开(公告)号：US07790564B2
公开(公告)日：2010-09-07
申请号：US12108851
申请日：2008-04-24
申请人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/331 , H01L21/76 , H01L21/22 , H01L21/38 , H01L21/762
CPC分类号： H01L21/7624
摘要： Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer.
摘要翻译：在绝缘体上半导体衬底中制造器件结构的方法。该方法包括在衬底器件层中形成第一隔离区，该第一隔离区从器件层的顶表面延伸到第一深度，并且在半导体层中形成第二隔离区，该半导体层从半导体层的顶表面延伸到第二隔离区深度大于第一深度。该方法还包括在垂直位于第一隔离区域和绝缘层之间的半导体层中形成器件结构的掺杂区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式