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1. 发明授权

US08877603B2 Semiconductor-on-oxide structure and method of forming 有权
标题翻译：半导体氧化物结构及其形成方法
公开(公告)号：US08877603B2
公开(公告)日：2014-11-04
申请号：US13435056
申请日：2012-03-30
申请人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, Jr. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L21/76 , H01L21/30 , H01L21/46
CPC分类号： H01L29/06 , H01L21/76254
摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
摘要翻译：公开了形成这种结构的半导体 - 氧化物结构和相关方法。在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

2. 发明授权

US08815671B2 Use of contacts to create differential stresses on devices 有权
标题翻译：使用触点在器件上产生差分应力
公开(公告)号：US08815671B2
公开(公告)日：2014-08-26
申请号：US12892474
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76834 , H01L21/76877 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/665 , H01L29/6653 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

3. 发明申请

US20130256830A1 SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING 有权
标题翻译：半导体氧化物结构及其形成方法
公开(公告)号：US20130256830A1
公开(公告)日：2013-10-03
申请号：US13435056
申请日：2012-03-30
申请人： John E. Barth, JR. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
发明人： John E. Barth, JR. , Herbert L. Ho , Babar A. Khan , Kirk D. Peterson
IPC分类号： H01L23/532 , H01L21/768 , H01L29/06 , H01L21/762
CPC分类号： H01L29/06 , H01L21/76254
摘要： Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.
摘要翻译：公开了形成这种结构的半导体 - 氧化物结构和相关方法。在一种情况下，一种方法包括：在衬底上形成第一介质层; 在所述第一介电层上形成第一导电层，所述第一导电层包括金属或硅化物之一; 在所述第一导电层上形成第二电介质层; 将施主晶片键合到第二介电层，施主晶片包括施主电介质和半导体层; 切割施主晶片以去除施主半导体层的一部分; 从所述施主半导体层的未移动部分形成至少一个半导体隔离区; 以及通过施主电介质和第二介电层形成与第一导电层的接触。

4. 发明申请

US20130170012A1 MICROMIRRORS FOR COLOR ELECTRONIC PAPER AND DESIGN STRUCTURES FOR SAME 有权
标题翻译：用于彩色电子纸的微型计算机及其设计结构
公开(公告)号：US20130170012A1
公开(公告)日：2013-07-04
申请号：US13343395
申请日：2012-01-04
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： G02B26/00
CPC分类号： G02B26/0841 , G02B5/201
摘要： Direct view color displays and design structures of direct view color displays. The direct view displays include micromirrors having un-tilted and tilted states and multiple color filters or color reflectors.
摘要翻译：直观视图彩色显示器和直观视图彩色显示器的设计结构。直视图显示器包括具有不倾斜和倾斜状态的微镜，以及多个滤色器或彩色反射器。

5. 发明授权

US08347260B2 Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage 有权
标题翻译：基于可制造性，测试覆盖和可选地诊断覆盖的组合来设计集成电路的方法
公开(公告)号：US08347260B2
公开(公告)日：2013-01-01
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M. P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M. P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F11/22
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

6. 发明申请

US20120074502A1 USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES 有权
标题翻译：使用联系人创建设备上的差别应力
公开(公告)号：US20120074502A1
公开(公告)日：2012-03-29
申请号：US12892474
申请日：2010-09-28
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Robert R. Robison
IPC分类号： H01L25/11 , H01L21/77
CPC分类号： H01L21/823807 , H01L21/28518 , H01L21/76834 , H01L21/76877 , H01L21/823814 , H01L21/823871 , H01L23/485 , H01L29/665 , H01L29/6653 , H01L29/7845 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.
摘要翻译：这里公开了使用触点在集成电路（IC）芯片中的器件上产生差分应力的各种方法和结构。公开了具有p型场效应晶体管（PFET）和n型场效应晶体管（NFET）的IC芯片。本发明的一个实施例包括通过改变用于形成PFET和NFET触点的沉积条件（例如，沉积填充材料的温度）以及填充材料沉积的速率来产生该微分应力。在另一个实施例中，通过用不同的材料填充触点来产生差分应力，这些材料将由于不同的热膨胀系数而赋予差压。在另一个实施例中，通过在NFET触点和/或PFET触点内包括硅化物层来产生差分应力。

7. 发明授权

US07799609B2 Method of manufacturing dual orientation wafers 有权
标题翻译：制造双取向晶圆的方法
公开(公告)号：US07799609B2
公开(公告)日：2010-09-21
申请号：US11955436
申请日：2007-12-13
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Alain Loiseau , Kirk D. Peterson
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Alain Loiseau , Kirk D. Peterson
IPC分类号： H01L21/00 , H01L29/04
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/8252
摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.
摘要翻译：公开了制造双取向晶片的方法。在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。另外的隔离结构形成在沟槽内和半导体层内的硅材料内。对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

8. 发明申请

US20080029844A1 ANTI-FUSE STRUCTURE OPTIONALLY INTEGRATED WITH GUARD RING STRUCTURE 审中-公开
标题翻译：防腐结构选择性地与保护环结构集成
公开(公告)号：US20080029844A1
公开(公告)日：2008-02-07
申请号：US11462070
申请日：2006-08-03
申请人： James W. Adkisson , Jeffrey P. Gambino , Kirk D. Peterson , William R. Tonti
发明人： James W. Adkisson , Jeffrey P. Gambino , Kirk D. Peterson , William R. Tonti
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure and a related method for fabricating the anti-fuse structure include a doped well within a semiconductor substrate. A first aperture and a second aperture that expose the doped well are located within a dielectric layer located over the semiconductor substrate and the doped well. A first conductor layer is located within the first aperture and a second conductor layer is located within the second aperture. At least a first anti-fuse material layer contacts the first conductor layer. The first conductor layer and the second conductor layer may comprise doped conductor materials that upon fusing of the anti-fuse structure provide an anti-fuse diode or an anti-fuse resistor.
摘要翻译：用于制造抗熔丝结构的反熔丝结构和相关方法包括半导体衬底内的掺杂阱。暴露掺杂阱的第一孔径和第二孔径位于位于半导体衬底和掺杂阱上方的电介质层内。第一导体层位于第一孔内，第二导体层位于第二孔内。至少第一反熔丝材料层接触第一导体层。第一导体层和第二导体层可以包括掺杂的导体材料，其在抗熔丝结构融合时提供抗熔丝二极管或抗熔丝电阻器。

9. 发明授权

US07315066B2 Protect diodes for hybrid-orientation substrate structures 失效
标题翻译：用于混合取向衬底结构的保护二极管
公开(公告)号：US07315066B2
公开(公告)日：2008-01-01
申请号：US10908926
申请日：2005-06-01
申请人： James W. Atkisson , Jeffrey P. Gambino , Alain Loiseau , Kirk D. Peterson
发明人： James W. Atkisson , Jeffrey P. Gambino , Alain Loiseau , Kirk D. Peterson
IPC分类号： H01L23/62
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/0255 , H01L27/0922 , H01L27/1207 , H01L29/045
摘要： A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.
摘要翻译：一种半导体结构及其形成方法。该结构包括具有不同晶格取向的第一和第二硅区的混合取向嵌段。第一硅区域直接在块上，而第二硅区域通过电介质区域与块物理隔离。第一和第二晶体管分别形成在第一和第二区域上。此外，在第一掺杂放电预防结构防止对第一晶体管的放电损坏的块上形成第一和第二掺杂放电预防结构，而第二掺杂放电预防结构在等离子体处理期间防止对第二晶体管的放电损坏。在第一和第二晶体管的正常操作期间，第一和第二放电预防结构表现得像电介质区域。

10. 发明授权

US07232711B2 Method and structure to prevent circuit network charging during fabrication of integrated circuits 失效
标题翻译：在集成电路制造过程中防止电路网络充电的方法和结构
公开(公告)号：US07232711B2
公开(公告)日：2007-06-19
申请号：US10908720
申请日：2005-05-24
申请人： Jeffrey P. Gambino , Kirk D. Peterson
发明人： Jeffrey P. Gambino , Kirk D. Peterson
IPC分类号： H01L21/82 , H01L21/326 , H01L21/479
CPC分类号： H01L27/1203 , H01L23/5256 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.
摘要翻译：集成电路及其制造方法。该集成电路包括：一个或多个配电网络; 一个或多个地面分配网络; 一个或多个数据网络; 并且将相同或不同网络的电力，地线或数据线临时并电连接在一起，从由一个或多个配电网络，一个或多个配电网络，一个或多个配电网络组成的组中选择的相同或不同的网络，更多数据网络及其组合。

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