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51. 发明授权

US08911775B2 pH-sensitive block copolymer forming polyionic complex micelles and drug or protein carrier using the same 有权
标题翻译：形成多聚离子复合物胶束的pH敏感嵌段共聚物和使用其的药物或蛋白质载体
公开(公告)号：US08911775B2
公开(公告)日：2014-12-16
申请号：US12842388
申请日：2010-07-23
申请人： Doo Sung Lee , Bong Sup Kim , Jung Hee Lee , Guanghui Gao
发明人： Doo Sung Lee , Bong Sup Kim , Jung Hee Lee , Guanghui Gao
IPC分类号： A61K38/38 , C08G73/06 , A61K9/127 , A61P35/00 , A61P9/10 , A61P29/00 , A61P19/02 , C08L71/02 , C08F299/02 , B82Y5/00 , C08F290/06 , A61K9/107
CPC分类号： C08F290/062 , A61K9/1075 , B82Y5/00 , C08F299/024 , C08G2261/126 , C08L71/02 , C08L2201/06 , C08L2203/02 , C08L2205/05 , C08L67/00
摘要： Disclosed is a pH-sensitive block copolymer that forms polyionic complex micelles. The block copolymer is prepared by copolymerization of (a) a polyethylene glycol compound, (b) a poly(amino acid) compound, and (c) a heterocyclic alkyl amine compound having the ability to induce the formation of ionic complexes. Further disclosed is a drug or protein carrier using the block copolymer.
摘要翻译：公开了形成聚离子复合物胶束的pH敏感性嵌段共聚物。嵌段共聚物通过（a）聚乙二醇化合物，（b）聚（氨基酸）化合物和（c）具有诱导形成离子络合物的能力的杂环烷基胺化合物的共聚制备。还公开了使用嵌段共聚物的药物或蛋白质载体。

52. 发明授权

US08735940B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08735940B2
公开(公告)日：2014-05-27
申请号：US12965640
申请日：2010-12-10
申请人： Woo Chul Jeon , Ki Yeol Park , Young Hwan Park , Jung Hee Lee
发明人： Woo Chul Jeon , Ki Yeol Park , Young Hwan Park , Jung Hee Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/66462
摘要： There are provided a semiconductor device and a method for manufacturing the same. The semiconductor device according to the present invention includes a base substrate; a semiconductor layer that includes a receiving groove and a protrusion part formed on the base substrate, a first carrier injection layer and at least two insulating layers formed to traverse the first carrier injection layer formed in the semiconductor layer, and a second carrier injection layer spaced apart from the first carrier injection layer formed on the protrusion part; a source electrode and a drain electrode that are disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode that is insulated from the source electrode and the drain electrode and has a recess part recessed into the receiving groove, wherein the lowest end portion of the receiving groove contacts the uppermost layer of the first carrier injection layer and the insulating pattern disposed at the innermost side of the semiconductor layer among the insulating patterns traverses the entire layer forming the first carrier injection layer and is disposed at the outer side of both side end portions in the thickness direction of the receiving groove.
摘要翻译：提供了一种半导体器件及其制造方法。根据本发明的半导体器件包括：基底; 半导体层，其包括形成在所述基底基板上的接收槽和突出部，第一载流子注入层和形成为穿过形成在所述半导体层中的所述第一载流子注入层的至少两个绝缘层，以及间隔开的第二载流子注入层除了形成在突出部上的第一载流子注入层之外; 源电极和漏电极，其设置成在半导体层上彼此间隔开; 以及与源电极和漏电极绝缘并且具有凹入到接收槽中的凹部的栅电极，其中接收槽的最低端部接触第一载流子注入层的最上层，并且布置的绝缘图案在绝缘图案中的半导体层的最内侧穿过形成第一载流子注入层的整个层，并且设置在接收槽的厚度方向上的两个侧端部的外侧。

53. 发明授权

US08611345B2 Apparatus and method for processing multi-layer packet 有权
标题翻译：多层数据包处理装置及方法
公开(公告)号：US08611345B2
公开(公告)日：2013-12-17
申请号：US12903680
申请日：2010-10-13
申请人： Dong Myoung Baek , Bhum Cheol Lee , Jung Hee Lee , Sang Yoon Oh , Seung-Woo Lee
发明人： Dong Myoung Baek , Bhum Cheol Lee , Jung Hee Lee , Sang Yoon Oh , Seung-Woo Lee
IPC分类号： H04L12/28
CPC分类号： H04L43/18 , H04L69/12 , H04L69/22 , H04L69/32
摘要： Provided is an apparatus and method for inspecting a multi-layer packet. The apparatus may include a lower layer processing unit to generate lower layer hash information based on a lower layer packet of the multi-layer packet, and to perform a first processing with respect to a flow of the multi-layer packet, in association with the generated lower layer hash information, and a higher layer preprocessing unit to perform a second processing with respect to a flow of the multi-layer packet where the first processing is performed, in association with the lower layer hash information.
摘要翻译：提供了一种用于检查多层分组的装置和方法。该装置可以包括下层处理单元，用于基于多层分组的较低层分组生成下层散列信息，并且与多层分组的流程相关联地执行关于多层分组的流的第一处理生成的下层哈希信息，以及较高层预处理单元，与下层哈希信息相关联地执行关于执行第一处理的多层分组的流的第二处理。

54. 发明授权

US08525231B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08525231B2
公开(公告)日：2013-09-03
申请号：US12965649
申请日：2010-12-10
申请人： Ki Yeol Park , Woo Chul Jeon , Young Hwan Park , Jung Hee Lee
发明人： Ki Yeol Park , Woo Chul Jeon , Young Hwan Park , Jung Hee Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L29/0649 , H01L29/2003 , H01L29/365 , H01L29/4236 , H01L29/66462 , H01L29/78681
摘要： There is provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer having a receiving groove, a protrusion part, a first carrier injection layer, at least two insulating patterns, and a second carrier injection layer provided on the base substrate, the insulating patterns being disposed to traverse the first carrier injection layer and the second carrier injection layer being spaced apart from the first carrier injection layer and disposed on a lower portion of the protrusion part; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part recessed into the receiving groove, wherein a lowest portion of the receiving groove contacts an uppermost layer of the first carrier injection layer or is disposed above the uppermost layer thereof, and an insulating pattern, disposed at an innermost portion of the semiconductor layer among the insulating patterns, traverses the first carrier injection layer and is disposed at the outside of both sides of the receiving groove in a thickness direction thereof.
摘要翻译：提供了一种半导体器件及其制造方法。半导体器件包括：基底; 具有接收槽的半导体层，突起部分，第一载流子注入层，至少两个绝缘图案和设置在基底基板上的第二载流子注入层，绝缘图案设置成穿过第一载流子注入层和第二载体注入层与第一载体注入层间隔开并设置在突出部分的下部; 源电极和漏电极，设置成在半导体层上彼此间隔开; 以及与源电极和漏电极绝缘的栅电极，并且具有凹入到所述接收槽中的凹部，其中所述接收槽的最下部接触所述第一载流子注入层的最上层，或者设置在所述第一载流子注入层的最上层并且绝缘图案设置在绝缘图案中的半导体层的最内部，穿过第一载流子注入层，并且沿着其厚度方向设置在容纳槽的两侧的外侧。

55. 发明授权

US08381145B2 Method and apparatus for analyzing fault behavior of a software design model 有权
标题翻译：分析软件设计模型的故障行为的方法和装置
公开(公告)号：US08381145B2
公开(公告)日：2013-02-19
申请号：US12912429
申请日：2010-10-26
申请人： Sachoun Park , Jung Hee Lee
发明人： Sachoun Park , Jung Hee Lee
IPC分类号： G06F17/50
CPC分类号： G06F11/3608
摘要： An apparatus for analyzing a fault behavior, includes a satisfiability modulo theories (SMT) conversion block for performing SMT conversion with respect to a protocol state machine diagram and a sequence diagram of a software design model. Further, the apparatus for analyzing the fault behavior includes an SMT processing block for performing a SMT processing using respective logic formulas corresponding to the protocol state machine diagram and the sequence diagram and outputted from the SMT conversion block, and determining whether the result of the SMT processing is satisfied to output an occurrable behavior scenario when the result of the SMT processing is satisfied.
摘要翻译：用于分析故障行为的装置包括用于执行关于协议状态机图的SMT转换的可满足的模理论（SMT）转换块和软件设计模型的序列图。此外，用于分析故障行为的装置包括：SMT处理块，用于使用与协议状态机图和序列图对应的各自的逻辑公式执行SMT处理，并从SMT转换块输出，并且确定SMT的结果当满足SMT处理的结果时，满足输出可发生的行为场景的处理。

56. 发明授权

US08361816B2 Method of manufacturing vertical gallium nitride based light emitting diode 有权
标题翻译：制造垂直氮化镓基发光二极管的方法
公开(公告)号：US08361816B2
公开(公告)日：2013-01-29
申请号：US11634106
申请日：2006-12-06
申请人： Jae Hoon Lee , Jung Hee Lee , Hyun Ick Cho , Dae Kil Kim , Jae Chul Ro
发明人： Jae Hoon Lee , Jung Hee Lee , Hyun Ick Cho , Dae Kil Kim , Jae Chul Ro
IPC分类号： H01L21/00
CPC分类号： H01L33/007 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L33/22
摘要： A method of manufacturing a vertical GaN-based LED includes forming a nitride-based buffer layer on a silicon substrate; sequentially forming a p-type GaN layer, an active layer, and an n-type GaN layer on the nitride-based buffer layer; forming an n-electrode on the n-type GaN layer; forming a plating seed layer on the n-electrode; forming a structure supporting layer on the plating seed layer; removing the silicon substrate through wet etching and forming roughness on the surface of the p-type GaN layer through over-etching; and forming a p-electrode on the p-type GaN layer having the roughness formed.
摘要翻译：制造垂直GaN基LED的方法包括在硅衬底上形成氮化物基缓冲层; 在氮化物基缓冲层上依次形成p型GaN层，有源层和n型GaN层; 在n型GaN层上形成n电极; 在n电极上形成电镀种子层; 在电镀种子层上形成结构支撑层; 通过湿蚀刻去除硅衬底，并通过过蚀刻在p型GaN层的表面上形成粗糙度; 在形成有粗糙度的p型GaN层上形成p电极。

57. 发明授权

US08319308B2 Semiconductor device and method for manufacturing of the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08319308B2
公开(公告)日：2012-11-27
申请号：US12654897
申请日：2010-01-07
申请人： Woo Chul Jeon , Jung Hee Lee , Young Hwan Park , Ki Yeol Park
发明人： Woo Chul Jeon , Jung Hee Lee , Young Hwan Park , Ki Yeol Park
IPC分类号： H01L21/322 , H01L29/47
CPC分类号： H01L29/0692 , H01L29/861 , H01L29/872
摘要： The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode.
摘要翻译：本发明提供一种半导体器件，包括：基底; 设置在所述基底基板上的第一半导体层; 设置在第一半导体层的中心区域上的第一欧姆电极; 在所述第一半导体层的边缘区域上具有围绕所述第一欧姆电极的环形形状的第二欧姆电极; 插入在所述第一欧姆电极和所述第一半导体层之间的第二半导体层; 以及肖特基电极部件，其覆盖中心区域上的第一欧姆电极，并且与第二欧姆电极间隔开。

58. 发明授权

US08316077B2 Apparatus and method for parallel-processing data flow 失效
标题翻译：并行处理数据流的装置和方法
公开(公告)号：US08316077B2
公开(公告)日：2012-11-20
申请号：US12912134
申请日：2010-10-26
申请人： Dong Myoung Baek , Bhum Cheol Lee , Jung Hee Lee , Sang Yoon Oh , Seung-Woo Lee
发明人： Dong Myoung Baek , Bhum Cheol Lee , Jung Hee Lee , Sang Yoon Oh , Seung-Woo Lee
IPC分类号： G06F15/16
CPC分类号： G06F9/5027 , H04L47/2483
摘要： Provided is a data flow-parallel processing apparatus and method. The data flow-parallel processing apparatus may include a lower layer processing unit to identify a flow of inputted first data, a distribution unit to select, from among a plurality of upper layer processing units, an upper layer processing unit corresponding to the flow, and to transmit the first data to the selected upper layer processing unit, and an upper layer processing unit to process an upper layer packet of the first data, based on a local memory corresponding to the flow from among a plurality of local memories.
摘要翻译：提供了一种数据流并行处理装置和方法。数据流并行处理装置可以包括：识别输入的第一数据的流的下层处理单元，从多个上层处理单元中选择与流相对应的上层处理单元的分发单元，以及基于与多个本地存储器中的流相对应的本地存储器，将第一数据发送到所选择的上层处理单元和上层处理单元，以处理第一数据的上层分组。

59. 发明申请

US20120007049A1 NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：基于氮化物的半导体器件及其制造方法
公开(公告)号：US20120007049A1
公开(公告)日：2012-01-12
申请号：US12917812
申请日：2010-11-02
申请人： Woo Chul JEON , Ki Yeol Park , Jung Hee Lee , Young Hwan Park
发明人： Woo Chul JEON , Ki Yeol Park , Jung Hee Lee , Young Hwan Park
IPC分类号： H01L29/778 , H01L21/329 , H01L21/335 , H01L29/15
CPC分类号： H01L29/872 , B82Y10/00 , H01L27/0605 , H01L27/0629 , H01L27/095 , H01L29/10 , H01L29/1075 , H01L29/152 , H01L29/2003 , H01L29/7786 , H01L29/861
摘要： The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.
摘要翻译：本发明提供一种氮化物类半导体器件。所述氮化物系半导体器件包括：具有二极管结构的基极基板; 设置在基底基板上的外延生长膜; 以及设置在外延生长膜上的电极部分，其中所述二极管结构包括：第一类型半导体层; 以及第二类型半导体层，其设置在所述第一类型半导体层内并且具有被所述第一类型半导体层覆盖的两侧。

60. 发明申请

US20110246954A1 METHOD AND APPARATUS FOR ANALYZING FAULT BEHAVIOR 有权
标题翻译：用于分析故障行为的方法和装置
公开(公告)号：US20110246954A1
公开(公告)日：2011-10-06
申请号：US12912429
申请日：2010-10-26
申请人： Sachoun PARK , Jung Hee LEE
发明人： Sachoun PARK , Jung Hee LEE
IPC分类号： G06F17/50
CPC分类号： G06F11/3608
摘要： An apparatus for analyzing a fault behavior, includes a satisfiability modulo theories (SMT) conversion block for performing SMT conversion with respect to a protocol state machine diagram and a sequence diagram of a software design model. Further, the apparatus for analyzing the fault behavior includes an SMT processing block for performing a SMT processing using respective logic formulas corresponding to the protocol state machine diagram and the sequence diagram and outputted from the SMT conversion block, and determining whether the result of the SMT processing is satisfied to output an occurrable behavior scenario when the result of the SMT processing is satisfied.
摘要翻译：用于分析故障行为的装置包括用于执行关于协议状态机图的SMT转换的可满足的模理论（SMT）转换块和软件设计模型的序列图。此外，用于分析故障行为的装置包括：SMT处理块，用于使用与协议状态机图和序列图对应的各自的逻辑公式执行SMT处理，并从SMT转换块输出，并且确定SMT的结果当满足SMT处理的结果时，满足输出可发生的行为场景的处理。

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