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51. 发明授权

US09143033B2 Hysteretic power converter with calibration circuit 有权
标题翻译：具有校准电路的迟滞功率转换器
公开(公告)号：US09143033B2
公开(公告)日：2015-09-22
申请号：US12956630
申请日：2010-11-30
申请人： Chia-Liang Tai , Alan Roth , Eric Soenen
发明人： Chia-Liang Tai , Alan Roth , Eric Soenen
IPC分类号： G05F1/00 , H02M3/156 , G05F1/40 , G05F1/10
CPC分类号： G05F1/575 , G01R1/203 , G05F1/00 , G05F1/10 , G05F1/40 , G05F1/56 , H02M3/156
摘要： A hysteretic power converter includes a comparator, a calibration circuit, and an output node having an output voltage. The calibration circuit is configured to supply a calibrated voltage to the comparator. The comparator controls the output voltage based on the calibrated voltage and a feedback voltage representing at least a portion of the output voltage.
摘要翻译：迟滞功率转换器包括比较器，校准电路和具有输出电压的输出节点。校准电路被配置为向比较器提供经校准的电压。比较器基于校准的电压和表示输出电压的至少一部分的反馈电压来控制输出电压。

52. 发明授权

US09076577B2 Resistor arrangement and method of use 有权
标题翻译：电阻布置及使用方法
公开(公告)号：US09076577B2
公开(公告)日：2015-07-07
申请号：US13619225
申请日：2012-09-14
申请人： Alan Roth , Alexander Kalnitsky , Chien-Chung Tseng
发明人： Alan Roth , Alexander Kalnitsky , Chien-Chung Tseng
IPC分类号： H01C7/10 , H01C7/13 , H01C13/02 , H01C1/16
CPC分类号： H01C13/02 , H01C1/16
摘要： This disclosure relates to a semiconductor device including resistor arrangement including a first resistor electrically connected to a ground voltage and a second resistor in direct physical contact with the first resistor. The second resistor is configured to receive a temperature independent current and the second resistor has thermal properties similar to those of the first resistor. This disclosure also relates to a semiconductor device including a load configured to receive an operating voltage and a voltage source configured to supply the operating voltage. The semiconductor device further includes a resistor arrangement between the load and the voltage source. This disclosure also relates to a method of using a resistor arrangement to calculate an operating current.
摘要翻译：本公开涉及包括电阻器装置的半导体器件，该电阻器装置包括电连接到接地电压的第一电阻器和与第一电阻器直接物理接触的第二电阻器。第二电阻器被配置为接收与温度无关的电流，并且第二电阻器具有与第一电阻器类似的热特性。本公开还涉及包括被配置为接收工作电压的负载和被配置为提供工作电压的电压源的半导体器件。半导体器件还包括负载和电压源之间的电阻器配置。本公开还涉及使用电阻器装置来计算工作电流的方法。

53. 发明授权

US09013341B2 Noise shaping for digital pulse-width modulators 有权
标题翻译：数字脉宽调制器的噪声整形
公开(公告)号：US09013341B2
公开(公告)日：2015-04-21
申请号：US13619034
申请日：2012-09-14
申请人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi , Justin Gaither
发明人： Eric Soenen , Alan Roth , Martin Kinyua , Justin Shi , Justin Gaither
IPC分类号： H03M3/00 , H03H17/00
CPC分类号： H03M3/344 , H03H17/00 , H03M3/00 , H03M3/464
摘要： A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.
摘要翻译：包括模数转换器（ADC）的电路。 ADC配置为接收模拟反馈信号和模拟输入信号并产生数字输出。电路还包括噪声整形器。噪声整形器被配置为截断数字输出并产生具有比数字输出低的位数的噪声整形器输出，并且形成在截断期间产生的量化噪声。电路还包括脉宽调制数模转换器（PWM DAC）。 PWM DAC被配置为处理噪声整形器输出的截断数字输出并产生PWM DAC输出。

54. 发明申请

US20140211905A1 RATIO METER OF A THERMAL SENSOR 有权
标题翻译：热传感器的比率表
公开(公告)号：US20140211905A1
公开(公告)日：2014-07-31
申请号：US13754151
申请日：2013-01-30
申请人： Mei-Chen CHUANG , Jui-Cheng HUANG , Alan ROTH
发明人： Mei-Chen CHUANG , Jui-Cheng HUANG , Alan ROTH
IPC分类号： G01K1/00
CPC分类号： G01K1/00 , G01K1/02 , G01K7/01 , G01K7/34 , G01K2219/00
摘要： A ratio meter includes a converter circuit, a first counter, a delay circuit, and a second counter. The converter circuit is configured to receive a temperature-independent signal, to convert the received temperature-independent signal into a first frequency signal during a first phase, to receive a temperature-dependent signal, and to convert the temperature-dependent signal into a second frequency signal during a second phase. The first counter is configured to receive the first frequency signal and to generate a control signal by counting a predetermined number of pulses of the first frequency signal count. The delay circuit is configured to delay the control signal for a predetermined time delay. The second counter is configured to receive the second frequency signal and to generate a count value by counting the second frequency signal.
摘要翻译：比率计包括转换器电路，第一计数器，延迟电路和第二计数器。转换器电路被配置为接收温度独立信号，以在第一阶段期间将接收到的与温度无关的信号转换为第一频率信号，以接收依赖于温度的信号，并将温度相关信号转换为第二频率信号频率信号在第二阶段。第一计数器被配置为接收第一频率信号并且通过对预定数量的第一频率信号计数的脉冲进行计数来产生控制信号。延迟电路被配置为延迟控制信号达预定的时间延迟。第二计数器被配置为接收第二频率信号并且通过对第二频率信号进行计数来产生计数值。

55. 发明授权

US08618784B2 Regulator control circuits, switching regulators, systems, and methods for operating switching regulators 有权
标题翻译：调节器控制电路，开关稳压器，系统和操作开关稳压器的方法
公开(公告)号：US08618784B2
公开(公告)日：2013-12-31
申请号：US12750149
申请日：2010-03-30
申请人： Justin Shi , Alan Roth , Eric Soenen
发明人： Justin Shi , Alan Roth , Eric Soenen
IPC分类号： G05F1/00
CPC分类号： H02M1/08 , H02M3/07
摘要： A regulator control circuit includes a high side driver that is configured to receive a supply voltage. A capacitor is configured to store charges. A first transistor is coupled between the capacitor at a first node and a gate of a high side driver at a second node. The first node is capable of being boosted to a voltage to operate the first transistor at a saturation mode for a charge sharing between the first node and the second node so as to substantially turn on the high side driver.
摘要翻译：调节器控制电路包括被配置为接收电源电压的高侧驱动器。配置电容器来存储电荷。第一晶体管耦合在第一节点处的电容器和第二节点处的高侧驱动器的栅极之间。第一节点能够被升压到电压以在饱和模式下操作第一晶体管，用于在第一节点和第二节点之间的电荷共享，以便基本上接通高侧驱动器。

56. 发明授权

US08441235B2 Battery charger digital control circuit and method 有权
标题翻译：电池充电器数字控制电路及方法
公开(公告)号：US08441235B2
公开(公告)日：2013-05-14
申请号：US13032956
申请日：2011-02-23
申请人： Justin Shi , Eric Soenen , Alan Roth
发明人： Justin Shi , Eric Soenen , Alan Roth
IPC分类号： H02J7/00 , H03M3/00
CPC分类号： H02J7/0073 , H02M3/157
摘要： A digital controlled battery charger comprises a power converter, a voltage sensor, a current senor, a mode selector and a digital controller. The voltage sensor and current sensor detect the voltage of a rechargeable battery and the current flowing through the rechargeable battery respectively. The mode selector selects a feedback signal from either the output of the voltage sensor or the output of the current sensor. The digital controller receives the selected feedback signal and generates a pulse width modulated signal for the power converter. Additionally, the digital controller is capable of dynamically adjusting its coefficients so that the control loop can maintain a stable system when the battery charger operates in different battery charging phases.
摘要翻译：数字控制电池充电器包括功率转换器，电压传感器，电流传感器，模式选择器和数字控制器。电压传感器和电流传感器分别检测可充电电池的电压和流过可充电电池的电流。模式选择器从电压传感器的输出或电流传感器的输出中选择反馈信号。数字控制器接收所选择的反馈信号并产生用于功率转换器的脉宽调制信号。此外，数字控制器能够动态地调整其系数，使得当电池充电器在不同的电池充电阶段中操作时，控制回路可以维持稳定的系统。

57. 发明授权

US08296598B2 Double data rate output circuit and method 有权
标题翻译：双数据速率输出电路及方法
公开(公告)号：US08296598B2
公开(公告)日：2012-10-23
申请号：US13113550
申请日：2011-05-23
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G06F1/12 , H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

58. 发明申请

US20120146716A1 Apparatus for Controlling Slew Rate 有权
标题翻译：用于控制压摆率的装置
公开(公告)号：US20120146716A1
公开(公告)日：2012-06-14
申请号：US12964412
申请日：2010-12-09
申请人： Justin Shi , Alan Roth , Ying-Chih Hsu , Justin Gaither , Eric Soenen
发明人： Justin Shi , Alan Roth , Ying-Chih Hsu , Justin Gaither , Eric Soenen
IPC分类号： G05F1/10
CPC分类号： H03K17/163 , H02M2001/0029 , H03K2217/0081
摘要： An apparatus for controlling slew rate is coupled to two adjustable voltage rails. The output of the apparatus is coupled to the gate of a switching element. By employing two adjustable voltage rails, the slew rate of the switching element is proportional to the voltage difference between the first adjustable rail and the second adjustable rail. The slew rate control apparatus can be applied to a variety of switching elements including N channel Field Effect Transistors (NFETs), P channel Field Effect Transistors (PFETs), current mode logic circuits and level shifter circuits.
摘要翻译：用于控制转换速率的装置耦合到两个可调电压轨。该装置的输出耦合到开关元件的栅极。通过采用两个可调电压轨道，开关元件的转换速率与第一可调节轨道和第二可调节轨道之间的电压差成比例。压摆率控制装置可以应用于包括N沟道场效应晶体管（NFET），P沟道场效应晶体管（PFET），电流模式逻辑电路和电平移位器电路的各种开关元件。

59. 发明申请

US20120056659A1 INTEGRATED CIRCUITS FOR CONVERTING A HIGH VOLTAGE LEVEL TO A LOW VOLTAGE LEVEL 有权
标题翻译：用于将高电平电平转换为低电平电平的集成电路
公开(公告)号：US20120056659A1
公开(公告)日：2012-03-08
申请号：US12877535
申请日：2010-09-08
申请人： Mei-Chen CHUANG , Alan ROTH
发明人： Mei-Chen CHUANG , Alan ROTH
IPC分类号： H03K17/687 , H03K17/00
CPC分类号： H02M3/158 , G05F1/462 , H02M3/157 , H02M3/1588 , H05B33/0815 , Y02B70/1466
摘要： An integrated circuit includes a high side driver and a low side driver. The low side driver is electrically coupled with the high side driver. A circuit is electrically coupled with the high side driver and a first node between the high side driver and the low side driver. The circuit is configured to substantially turn off the high side driver if the high side driver leaves a cutoff region of the high side driver during a tri-state mode.
摘要翻译：集成电路包括高侧驱动器和低侧驱动器。低侧驱动器与高侧驱动器电耦合。电路与高侧驱动器和高侧驱动器和低侧驱动器之间的第一节点电耦合。如果高侧驱动器在三态模式期间离开高侧驱动器的截止区域，则该电路被配置为基本上关闭高侧驱动器。

60. 发明申请

US20110228626A1 SYNCHRONIZATION CIRCUIT AND METHOD WITH TRANSPARENT LATCHES 有权
标题翻译：同步电路的同步电路和方法
公开(公告)号：US20110228626A1
公开(公告)日：2011-09-22
申请号：US13113550
申请日：2011-05-23
申请人： Alan Roth , Oswald Becca , Pedro Ovalle
发明人： Alan Roth , Oswald Becca , Pedro Ovalle
IPC分类号： G11C8/00 , H03L7/00
CPC分类号： G06F5/08
摘要： A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.
摘要翻译：提出了用于将数据从输入时钟重新同步到输出时钟的同步电路。第一透明锁存器接收与输入时钟同步的数据。第二透明锁存器从第一透明锁存器接收数据，并输出取决于延迟的输出时钟的数据，延迟的输出时钟是延迟了插入延迟的输出时钟。输出锁存器从第二透明锁存器接收数据并将数据与输出时钟同步。

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