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41. 发明授权

US09096922B2 Silicon layers formed from polymer-modified liquid silane formulations 有权
标题翻译：由聚合物改性液体硅烷配方形成的硅层
公开(公告)号：US09096922B2
公开(公告)日：2015-08-04
申请号：US13503668
申请日：2010-10-18
申请人： Bernhard Stuetzel , Matthias Patz
发明人： Bernhard Stuetzel , Matthias Patz
IPC分类号： H01L29/04 , H01L31/20 , H01L31/036 , H01L31/0376 , H01L29/12 , H01L31/0312 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , C23C18/12 , C23C18/14 , H01L21/02
CPC分类号： C23C18/1204 , C09D183/16 , C23C18/122 , C23C18/14 , H01L21/0242 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02628
摘要： The invention relates to a formulation which contains at least one silane and at least one carbon polymer in a solvent, and to the production of a silicon layer on a substrate which is coated with such a formulation.
摘要翻译：本发明涉及一种在溶剂中含有至少一种硅烷和至少一种碳聚合物的制剂，以及在涂有这种制剂的基材上生产硅层。

42. 发明授权

US09082842B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09082842B2
公开(公告)日：2015-07-14
申请号：US14359761
申请日：2011-11-22
申请人： Yasuhiro Hirabayashi , Masaru Senoo
发明人： Yasuhiro Hirabayashi , Masaru Senoo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/78 , H01L29/739 , H01L29/40 , H01L29/423 , H01L29/06
CPC分类号： H01L29/78 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/861
摘要： A semiconductor device disclosed herein includes an insulated gate, a main and a sub trench conductors. The main and sub trench conductors are formed in the cell region, and have a conductor that is covered with an insulation film and fills a trench extending in a first direction. The sub trench is located, with respect to the main trench conductor, in a second direction perpendicularly crossing the first direction and extending from the cell region side to the non-cell region. Length of the sub trench conductor in the first direction is shorter than a length of the insulated gate in the first direction. Distance between the main and sub trench conductors is shorter than a distance between the main trench conductor and the insulated gate. At least a part of the sub trench conductor reaches a position deeper than a boundary between the first and second semiconductor regions.
摘要翻译：本文公开的半导体器件包括绝缘栅极，主沟道和次沟槽导体。主沟槽导体和副沟槽导体形成在单元区域中，并且具有被绝缘膜覆盖的导体，并填充沿第一方向延伸的沟槽。子沟槽相对于主沟槽导体沿与第一方向垂直的第二方向并且从单元区域侧延伸到非单元区域。第一方向上的副沟槽导体的长度比第一方向上的绝缘栅极的长度短。主沟槽导体和副沟槽导体之间的距离短于主沟道导体与绝缘栅之间的距离。子沟槽导体的至少一部分达到比第一和第二半导体区域之间的边界更深的位置。

43. 发明授权

US09064958B1 Multiple gate transistor architecture providing an accessible inner source-drain node 有权
标题翻译：多栅极晶体管架构提供可访问的内部源极 - 漏极节点
公开(公告)号：US09064958B1
公开(公告)日：2015-06-23
申请号：US13156016
申请日：2011-06-08
申请人： Christian Rye Iversen , Jason Yuxin Li
发明人： Christian Rye Iversen , Jason Yuxin Li
IPC分类号： H01L27/10 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/812 , H01L29/78
CPC分类号： H01L29/7831 , H01L27/0605 , H01L27/085 , H01L29/0692 , H01L29/41758 , H01L29/42316 , H01L29/4238 , H01L29/7786 , H01L29/8124
摘要： The present invention provides a multiple gate transistor architecture that provides an accessible inner source-drain (SD) node. The transistor architecture includes a source structure having multiple source fingers, which extend from a source bus, and a drain structure having multiple drain fingers, which extend from a drain bus. The fingers of the respective source and drain structures are interleaved wherein a meandering path is formed between the source and drain structures. Two or more gate structures run substantially parallel to one another along the meandering path between the source and drain structures. An SD structure is provided between each adjacent pair of gate structures and runs along the meandering path to form the SD node. An SD extension is coupled to the SD structure and accessible by other circuitry to allow a signal to be applied to the SD structure during operation.
摘要翻译：本发明提供了提供可访问的内部源 - 漏（SD）节点的多栅极晶体管架构。该晶体管结构包括具有多个源极指的源结构，其源极总线延伸，以及具有多个漏极指的漏极结，漏极指从漏极总线延伸。各个源极和漏极结构的指状物交错，其中在源极和漏极结构之间形成曲折的路径。两个或更多个栅极结构沿着源极和漏极结构之间的曲折路径基本上彼此平行地延伸。在每个相邻的栅结构对之间提供SD结构，并且沿着曲折路径延伸以形成SD节点。 SD扩展被耦合到SD结构，并且可被其他电路访问，以允许在操作期间将信号施加到SD结构。

44. 发明授权

US09064865B2 Mechanisms for forming gate dielectric layer 有权
标题翻译：形成栅极介电层的机理
公开(公告)号：US09064865B2
公开(公告)日：2015-06-23
申请号：US14052332
申请日：2013-10-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd
发明人： Liang-Chen Chi , Chia-Ming Tsai , Chin-Kun Wang , Jhih-Jie Huang , Miin-Jang Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/51 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28185 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/785
摘要： Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer.
摘要翻译：提供了用于形成半导体器件的机构的实施例。半导体器件包括在半导体衬底上的半导体衬底和氮化物缓冲层，并且氮化物缓冲层处于非晶态。半导体器件还包括在氮化物缓冲层上的结晶栅极介电层和结晶栅极介电层上的栅电极。

45. 发明授权

US09064079B2 Power layout for integrated circuits 有权
标题翻译：集成电路的电源布局
公开(公告)号：US09064079B2
公开(公告)日：2015-06-23
申请号：US14189181
申请日：2014-02-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chung-Chieh Yang
IPC分类号： H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , G06F17/50 , H01L23/522 , H01L23/528
CPC分类号： G06F17/5072 , G06F17/5068 , G06F2217/78 , H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically coupled to a second power supply voltage different from the first power supply voltage. The first power layer has conductive lines configured to surround a conductive element electrically connected to the second power layer.
摘要翻译：具有功率布局的集成电路至少包括一个电网单元。每个电网单元包括被配置为电耦合到第一电源电压的第一功率层和与第一功率层分离并被配置为电耦合到不同于第一电源电压的第二电源电压的第二功率层电压。第一功率层具有配置为围绕电连接到第二功率层的导电元件的导线。

46. 发明授权

US09029946B2 Power semiconductor device and method therefor 有权
标题翻译：功率半导体器件及其方法
公开(公告)号：US09029946B2
公开(公告)日：2015-05-12
申请号：US13903366
申请日：2013-05-28
申请人： Estivation Properties LLC
发明人： Robert Bruce Davies
IPC分类号： H01L31/119 , H01L31/062 , H01L27/02 , H01L23/047 , H01L23/051 , H01L23/36 , H01L23/66 , H01L23/00 , H01L29/423 , H01L29/66 , H01L29/78 , H01L21/28 , H01L21/762 , H01L23/10 , H01L23/482 , H01L23/498 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/417
CPC分类号： H01L27/0296 , H01L21/2815 , H01L21/32055 , H01L21/56 , H01L21/76224 , H01L21/768 , H01L21/76838 , H01L21/823412 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L21/823487 , H01L23/047 , H01L23/051 , H01L23/10 , H01L23/36 , H01L23/3675 , H01L23/4824 , H01L23/49844 , H01L23/552 , H01L23/66 , H01L24/06 , H01L24/83 , H01L25/50 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/4238 , H01L29/66681 , H01L29/66712 , H01L29/66719 , H01L29/66727 , H01L29/7811 , H01L29/7817 , H01L2223/6644 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/48091 , H01L2224/83193 , H01L2224/83801 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/0106 , H01L2924/01061 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/16152 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
摘要翻译：功率晶体管包括多个晶体管单元。每个晶体管单元具有耦合到覆盖第一主表面的第一电极互连区域的第一电极，耦合到覆盖第一主表面的控制电极互连区域的控制电极，以及耦合到覆盖第二主表面的第二电极互连区域的第二电极主要表面。每个晶体管单元在沟道区中具有近似恒定的掺杂浓度。电介质平台用作外延层的边缘终端以在其中保持基本上平面的等电位线。功率晶体管在以超过500兆赫的频率工作的射频应用中具有特别的用途，并耗散5瓦以上的功率。半导体管芯和封装被设计成使得功率晶体管能够在如此恶劣的条件下有效地工作。

47. 发明授权

US08994105B2 Power device integration on a common substrate 有权
公开(公告)号：US08994105B2
公开(公告)日：2015-03-31
申请号：US13887704
申请日：2013-05-06
申请人： Azure Silicon LLC
发明人： Jacek Korec
IPC分类号： H01L31/119 , H01L21/332
CPC分类号： H01L29/7393 , H01L27/1203 , H01L29/0626 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66325 , H01L29/66659 , H01L29/735 , H01L29/7835 , H01L29/7839 , H01L29/8605 , H01L29/8611 , H01L29/872 , H01L29/8725 , H01L29/945 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

48. 发明授权

US08994085B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08994085B2
公开(公告)日：2015-03-31
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
摘要翻译：一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

49. 发明授权

US08987818B1 Integrated MOS power transistor with thin gate oxide and low gate charge 有权
标题翻译：具有薄栅极氧化物和低栅极电荷的集成MOS功率晶体管
公开(公告)号：US08987818B1
公开(公告)日：2015-03-24
申请号：US13312827
申请日：2011-12-06
申请人： Joel Montgomery McGregor , Vishnu Khemka
发明人： Joel Montgomery McGregor , Vishnu Khemka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/402
摘要： A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The two polysilicon portions are separated by a gap. A lightly doped region is implanted in the substrate below the gap, thereby forming a bridge having the same doping type as the substrate body. The field plate also extends over a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor.
摘要翻译：分离栅功率晶体管包括横向配置的功率MOSFET，其包括掺杂硅衬底，形成在衬底的表面上的栅氧化层，以及形成在栅极氧化物层上的分裂多晶硅层。多晶硅层被切割成两个电隔离部分，第一部分形成位于衬底的沟道区上的多晶硅栅极，以及形成在衬底的过渡区域的一部分上的多晶硅场板的第二部分。两个多晶硅部分被间隙隔开。将轻掺杂区域注入到间隙下方的衬底中，从而形成具有与衬底本体相同的掺杂类型的桥。场板还在形成在衬底中的场氧化物填充沟槽上延伸。场板电耦合到分离栅功率晶体管的源极。

50. 发明授权

US08981477B2 Laterally diffused metal oxide semiconductor 有权
标题翻译：横向扩散金属氧化物半导体
公开(公告)号：US08981477B2
公开(公告)日：2015-03-17
申请号：US13833210
申请日：2013-03-15
申请人： Dongbu Hitek Co., Ltd.
发明人： Nam Chil Moon
IPC分类号： H01L29/76 , H01L29/74 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/58 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7816 , H01L29/063 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/42368 , H01L29/66681 , H01L29/66689
摘要： A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer.
摘要翻译：提供了横向扩散的金属氧化物半导体（LDMOS）器件及其制造方法。 LDMOS器件可以包括漂移区域中彼此间隔开预定间隔的漂移区域，源极区域和漏极区域，形成在源区域和漏极区域之间的漂移区域中的场绝缘层，以及第一 P-TOP区形成在场绝缘层下。 LDMOS器件还可以包括覆盖场绝缘层的一部分的栅极多晶硅，形成在栅极多晶硅上的栅电极和穿过栅电极，栅极多晶硅和场绝缘层的接触线。

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