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41. 发明申请

US20080124856A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080124856A1
公开(公告)日：2008-05-29
申请号：US11639344
申请日：2006-12-15
申请人： Sergey Pidin , Tamotsu Owada
发明人： Sergey Pidin , Tamotsu Owada
IPC分类号： H01L21/71 , H01L21/04
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A method of manufacturing a semiconductor device, in which a stress film having a large stress can be formed with high accuracy over a transistor. The method comprises the steps of: depositing a tensile stress film over the whole surface of a substrate having formed thereon an n-MOSFET; removing by etching the deposited stress film while leaving it on the n-MOSFET; and performing UV irradiation to the remaining stress film. By the UV irradiation, a tensile stress of the stress film is improved. Further, although the stress film is cured by the UV irradiation, occurrence of etching defects caused by the curing is prevented because the UV irradiation is performed after the etching. Thus, speeding-up and high quality of the n-MOSFET can be attained.
摘要翻译：一种制造半导体器件的方法，其中可以以高精度在晶体管上形成具有大应力的应力膜。该方法包括以下步骤：在其上形成有n-MOSFET的衬底的整个表面上沉积拉伸应力膜; 通过蚀刻沉积的应力膜同时将其留在n-MOSFET上去除; 对剩余的应力膜进行紫外线照射。通过UV照射，应力膜的拉伸应力提高。此外，虽然通过UV照射使应力膜固化，但是由于在蚀刻之后进行UV照射，因此防止了由固化引起的蚀刻缺陷的发生。因此，可以获得n-MOSFET的加速和高质量。

42. 发明申请

US20080111248A1 Flip Chip And Wire Bond Semiconductor Package 有权
标题翻译：倒装芯片和引线邦德半导体封装
公开(公告)号：US20080111248A1
公开(公告)日：2008-05-15
申请号：US11718396
申请日：2005-10-31
申请人： Chee Seng Foong , Aminuddin Ismail , Wai Yew Lo , Bee Hoon Liau , Jin-Mei Liu , Jian-Hong Wang , Jin-Zhong Yao , Fu-Bin Song
发明人： Chee Seng Foong , Aminuddin Ismail , Wai Yew Lo , Bee Hoon Liau , Jin-Mei Liu , Jian-Hong Wang , Jin-Zhong Yao , Fu-Bin Song
IPC分类号： H01L23/49 , H01L21/71
CPC分类号： H01L25/0657 , H01L24/73 , H01L25/0652 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48465 , H01L2224/49109 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06572 , H01L2225/06586 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/16152 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package (100, 150, 200, 250), and method of forming the package, including a substrate (102, 102′, 202, 202′) having an opening (104, 104′, 204, 204′) formed therein. Contact pads (112, 112′, 212, 212′) are formed about a periphery of the opening on a first side of the substrate (106, 106′, 206, 206′) and a second opposing side (132, 132′, 232, 232′) of the substrate. A flip chip die (120, 120′, 220, 220′) is mounted to the substrate, having an active side (114, 114′, 214, 214′) mounted on a first side of the substrate and in electrical communication with at least some of the contact pads formed on the first side of the substrate. At least one wire bond die (110, 110′, 210, 210′) is mounted through the opening, with a non-active side mounted on the active side of the flip chip die. The wire bond die is in electrical communication with at least some of the plurality of contact pads formed on the second opposing side of the substrate.
摘要翻译：一种形成封装的半导体封装（100,150,200,250）以及包括其中形成在其中的开口（104,104'，204,204'）的衬底（102,102'，202,202'）的方法，。在衬底（106,106'，206,206'）的第一侧上围绕开口的周边形成接触焊盘（112,112'，212,212'）和第二相对侧（132,132'， 232,232'）。倒装芯片模具（120,120'，220,220'）安装到衬底上，具有安装在衬底的第一侧上并与之电气连通的有源侧（114,114'，214,214'）在衬底的第一侧上形成的至少一些接触焊盘。至少一个引线接合管芯（110,110'，210,210'）穿过开口安装，其中非有源侧安装在倒装芯片裸片的有源侧上。引线接合管芯与形成在基板的第二相对侧上的多个接触焊盘中的至少一些电连接。

43. 发明授权

US07074682B2 Method for fabricating a semiconductor device having self aligned source (SAS) crossing trench 失效
标题翻译：用于制造具有自对准源（SAS）交叉沟槽的半导体器件的方法
公开(公告)号：US07074682B2
公开(公告)日：2006-07-11
申请号：US10951503
申请日：2004-09-27
申请人： Jum Soo Kim , Sung Mun Jung
发明人： Jum Soo Kim , Sung Mun Jung
IPC分类号： H01L21/71
CPC分类号： H01L27/11521 , H01L27/115
摘要： In order to provide a method for preventing the channel length from being shortened as well as reducing the SAS resistance, the semiconductor device according to the present invention is manufactured by forming continuous linear trench lines on a semiconductor substrate, forming gate oxide lines on the semiconductor substrate between the trench lines, forming gate lines on the trench lines and the gate oxide lines, the gate lines being substantially perpendicular to the trench lines, etching the gate oxide lines and trench lines positioned between the gate lines, to form an etched region forming self aligned sources (SASs) by implanting impurity ions into the etched region, forming spacers on sidewalls of the gate lines, and implanting impurity ions in the SAS region using the spacers as a mask.
摘要翻译：为了提供防止通道长度缩短以及降低SAS电阻的方法，根据本发明的半导体器件通过在半导体衬底上形成连续的线性沟槽线，在半导体衬底上形成栅极氧化物线沟槽线之间的衬底，在沟槽线上形成栅极线和栅极氧化物线，栅极线基本上垂直于沟槽线，蚀刻位于栅极线之间的栅极氧化物线和沟槽线，以形成蚀刻区域通过将杂质离子注入到蚀刻区域中形成自对准源（SAS），在栅极线的侧壁上形成间隔物，并且使用间隔物作为掩模将杂质离子注入到SAS区域中。

44. 发明授权

US5650357A Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same 失效
标题翻译：用于制造引线框电容器和使用其的电容耦合隔离电路的工艺
公开(公告)号：US5650357A
公开(公告)日：1997-07-22
申请号：US401033
申请日：1995-03-08
申请人： Robert C. Dobkin , Robert L. Reay
发明人： Robert C. Dobkin , Robert L. Reay
IPC分类号： H01L23/50 , H01L21/822 , H01L23/495 , H01L23/64 , H01L25/00 , H01L27/04 , H05K1/16 , H05K3/20 , H01L21/56 , H01L21/58 , H01L21/60 , H01L21/71
CPC分类号： H01L23/49575 , H01L23/49589 , H01L23/642 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/19041 , H05K1/162 , H05K3/202 , Y10S257/904 , Y10T29/435
摘要： A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.
摘要翻译：提供一种电容器，包括由常规集成电路封装中使用的引线框架结构的部分形成的第一和第二电极。电极用介电模塑材料封装，其在电极之间提供介电绝缘。还提供了一种低功率电容耦合数字隔离电路。该电路采用本发明的一对引线框电容器，并包括差分驱动器和接收器电路。接收机还可以包括可选的滤波器，以增加噪声和毛刺抗扰度。

45. 发明授权

US5576222A Method of making a semiconductor image sensor device 失效
标题翻译：制造半导体图像传感器装置的方法
公开(公告)号：US5576222A
公开(公告)日：1996-11-19
申请号：US324737
申请日：1994-10-18
申请人： Michio Arai , Masaaki Ikeda , Kazushi Sugiura , Nobuo Furukawa , Mitsufumi Kodama , Yukio Yamauchi , Naoya Sakamoto , Takeshi Fukada , Masaaki Hiroki , Ichirou Takayama
发明人： Michio Arai , Masaaki Ikeda , Kazushi Sugiura , Nobuo Furukawa , Mitsufumi Kodama , Yukio Yamauchi , Naoya Sakamoto , Takeshi Fukada , Masaaki Hiroki , Ichirou Takayama
IPC分类号： H01L31/20 , H01L27/14 , H01L21/336 , H01L21/71 , H01L27/01
CPC分类号： H01L31/20 , Y02E10/50
摘要： An image sensor (10) has a substrate (1), an active layer (3') having a source region and a drain region placed on said substrate (1), a gate insulation layer (4') placed on said active layer, and a gate electrode layer (5') on said gate insulation layer (4'). The active layer (3') is produced by the steps of producing amorphous silicon layer by using disilane gas (Si.sub.2 H.sub.6) through Low Pressure CVD process, and annealing said layer at 500.degree.-650.degree. C. for 4-50 hours in nitrogen gas atmosphere. The gate insulation layer (4') is produced through oxidation of the surface of the active layer at high temperature around 900.degree.-1100.degree. C. The oxidation process at high temperature improves the anneal process and improves the active layer. Thus, an image sensor with uniform characteristics is obtained with improved producing yield rate.
摘要翻译：图像传感器（10）具有基板（1），具有放置在所述基板（1）上的源极区域和漏极区域的有源层（3'），放置在所述有源层上的栅极绝缘层（4'），和栅极绝缘层（4'）上的栅电极层（5'）。有源层（3'）通过以下步骤制造：通过低压CVD法使用乙硅烷气体（Si 2 H 6）生成非晶硅层，并且在500-650℃下在氮气中退火所述层4-50小时大气层。栅极绝缘层（4'）通过在900〜-1100℃的高温下氧化活性层的表面而产生。高温下的氧化过程改善了退火过程并改善了活性层。因此，获得具有均匀特性的图像传感器，具有提高的生产率。

46. 发明授权

US11626366B2 Shielding using layers with staggered trenches 有权
公开(公告)号：US11626366B2
公开(公告)日：2023-04-11
申请号：US17360793
申请日：2021-06-28
申请人： Silicon Laboratories Inc.
发明人： Thomas C. Fowler , Jerome T. Wenske
IPC分类号： H01L23/522 , H01L21/71 , H01L23/00 , H01L49/02
摘要： An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

47. 发明授权

US10312130B2 LTPS array substrate, method for manufacturing the same, and display device 有权
公开(公告)号：US10312130B2
公开(公告)日：2019-06-04
申请号：US14897325
申请日：2015-08-05
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Yaru Jiang
IPC分类号： H01L21/71 , H01L27/15 , H01L27/32 , G02F1/13 , H01L27/12
摘要： An LTPS array substrate, a method for manufacturing the same, and a display device are disclosed. According to the method, a flat layer is formed on an electrode. The flat layer is formed through washing, baking to remove water, hydrophobization treatment, photoresist coating, drying in vacuum, pre-baking, exposing, developing, baking, and aching procedures in sequence, and the baking procedure comprises at least baking for twice with different temperatures. According to the method, the organic film of the flat layer can be preliminarily solidified. In this manner, the problem that the taper angle at via hole position is too small, which is resulted from the liquidity of photoresist material of the flat layer, can be solved.

48. 发明申请

US20180337044A1 Grafting Design for Pattern Post-Treatment in Semiconductor Manufacturing 审中-公开
公开(公告)号：US20180337044A1
公开(公告)日：2018-11-22
申请号：US15600037
申请日：2017-05-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Siao-Shan Wang , Ching-Yu Chang , Chin-Hsiang Lin
IPC分类号： H01L21/033 , H01L21/71 , H01L21/027
CPC分类号： H01L21/0332 , G03F7/40 , H01L21/0273
摘要： A method for lithography patterning includes forming an opening in a first layer over a substrate and coating a grafting solution over the first layer and filling in the opening. The grafting solution comprises a grafting compound and a solvent. The grafting compound comprises a grafting unit chemically bonded to a linking unit chemically bonded to a polymer backbone. The linking unit comprises an alkyl segment. The grafting unit is attachable to the first layer. The method further includes curing the grafting solution so that a first portion of the grafting compound is attached to a surface of the first layer, thereby forming a second layer over the surface of the first layer.

49. 发明申请

US20180144972A1 LTPS ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20180144972A1
公开(公告)日：2018-05-24
申请号：US14897325
申请日：2015-08-05
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Yaru JIANG
IPC分类号： H01L21/71 , H01L27/32 , H01L27/15
CPC分类号： H01L21/71 , G02F1/13 , H01L27/1248 , H01L27/1259 , H01L27/153 , H01L27/3241
摘要： An LTPS array substrate, a method for manufacturing the same, and a display device are disclosed. According to the method, a flat layer is formed on an electrode. The flat layer is formed through washing, baking to remove water, hydrophobization treatment, photoresist coating, drying in vacuum, pre-baking, exposing, developing, baking, and aching procedures in sequence, and the baking procedure comprises at least baking for twice with different temperatures. According to the method, the organic film of the flat layer can be preliminarily solidified. In this manner, the problem that the taper angle at via hole position is too small, which is resulted from the liquidity of photoresist material of the flat layer, can be solved.

50. 发明授权

US09925776B2 Method of manufacturing semiconductor chips for liquid discharge head 有权
公开(公告)号：US09925776B2
公开(公告)日：2018-03-27
申请号：US15623281
申请日：2017-06-14
申请人： CANON KABUSHIKI KAISHA
发明人： Tomohiro Takahashi , Toru Kawaguchi , Toshiyasu Sakai , Masataka Kato
IPC分类号： H01L21/71 , H01L21/304 , B41J2/16
CPC分类号： B41J2/1635 , B41J2/1603 , B41J2/162 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1632 , B41J2/1634
摘要： A method of manufacturing a plurality of semiconductor chips for a liquid discharge head from a substrate includes forming trenches of a linear form through etching from the second surface along intended cutting portions, forming modified portions in the substrate by irradiating a laser beam from the first surface side along the intended cutting portions, and splitting the substrate into the plurality of semiconductor chips for a liquid discharge head, by cutting the substrate with stress applied to the modified portions. The intended cutting portions include inclined portions extending in a direction inclined with respect to a crystal orientation plane of the substrate and uninclined portions extending in a direction along the crystal orientation plane of the substrate, and the trenches are formed at least along the inclined portions.

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