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41. 发明授权

US4985640A Apparatus for generating computer clock pulses 失效
标题翻译：用于产生计算机时钟脉冲的装置
公开(公告)号：US4985640A
公开(公告)日：1991-01-15
申请号：US472598
申请日：1990-04-04
申请人： Edward Grochowski , Rajesh Gupta
发明人： Edward Grochowski , Rajesh Gupta
IPC分类号： H03K5/15 , H03K5/151
CPC分类号： H03K5/151 , H03K5/15006
摘要： A circuit for generating a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator including apparatus for generating first and second pair of signals at half the frequency of the input signal generated by a crystal oscillator, the signals of each pair being of opposite phase to one another; apparatus for comparing a first signal of the first pair signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus for comparing the second signal of the first pair of signals with the one of the signals of the second pair of signals which is normally out of phase therewith to produce an output signal only when the two signals are in phase; apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair of signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases; apparatus for producing a pair of clock pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator; and apparatus responsive to the apparatus utilizing one of the output signals to lengthen the duty cycle of one of the first pair signals of opposite phases and the other of the output signals to shorten the duty cycle of the other of the first pair of signals of opposite phases for equalizing the duty cycle of the pair of closk pulses of opposite phases each having the same frequency as the frequency of an input signal generated by a crystal oscillator.
摘要翻译：一种用于产生相对相位的一对时钟脉冲的电路，每个时钟脉冲具有与由晶体振荡器产生的输入信号的频率相同的频率，该晶体振荡器包括用于产生第一和第二对信号的信号，所述第一和第二对信号的频率为由晶体振荡器，每对信号彼此相反; 用于将第一对信号的第一信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 用于将第一对信号的第二信号与通常与其相异相的第二对信号的信号之一进行比较以仅在两个信号同相时产生输出信号的装置; 利用所述输出信号之一来延长所述第一对相对相位信号中的一个的占空比以及所述输出信号中的另一个的占空比，以缩短所述第一对相对相位信号中另一个的占空比; 用于产生具有与由晶体振荡器产生的输入信号的频率相同频率的相反相位的一对时钟脉冲的装置; 以及响应于所述装置的设备，利用所述输出信号之一来延长所述第一对相对相位信号之一的占空比，并且输出信号中的另一个信号的占空比，以缩短所述第一对信号中另一个的相反的占空比用于均衡相位相对的一对闭合脉冲的占空比的相位，每个相位相位的频率与由晶体振荡器产生的输入信号的频率相同。

42. 发明授权

US4761568A Load-adapted clock generator in CMOS circuits 失效
标题翻译： CMOS电路中负载适配时钟发生器
公开(公告)号：US4761568A
公开(公告)日：1988-08-02
申请号：US91545
申请日：1987-08-31
申请人： Sabine Stronski
发明人： Sabine Stronski
IPC分类号： H03K3/02 , H03K5/151 , H03K19/0185 , H03K19/0948 , H03K5/13 , H03K3/01 , H03K3/284 , H03K5/00
CPC分类号： H03K19/0948 , H03K5/1515
摘要： A clock generator for CMOS circuits for producing two non-overlapping internal clocks or timing cycles at two clock outputs, the clock generator having a frequency divider energized by an oscillator and having an output side, and a bistable multivibrator connected to the output side of the frequency divider and having complementary outputs includes an equal number of inverter-driver stages connected to each of the complementary outputs and being controllable thereby, the driver stages being dimensioned asymmetrically.
摘要翻译：一种用于CMOS电路的时钟发生器，用于在两个时钟输出端产生两个不重叠的内部时钟或定时周期，时钟发生器具有由振荡器激励的并具有输出侧的分频器，以及连接到输出侧的双稳态多谐振荡器分频器并具有互补输出包括相等数量的反相器驱动器级，其连接到每个互补输出并且由此控制，驱动器级的尺寸不对称。

43. 发明授权

US4617477A Symmetrical output complementary buffer 失效
标题翻译：对称输出互补缓冲器
公开(公告)号：US4617477A
公开(公告)日：1986-10-14
申请号：US736554
申请日：1985-05-21
申请人： Michael V. DePaolis, Jr.
发明人： Michael V. DePaolis, Jr.
IPC分类号： H03K19/0948 , H03K5/151 , H03K19/003 , H03K19/017 , H03K19/094 , H03K3/86 , H03K17/693 , H03K19/20
CPC分类号： H03K5/151 , H03K19/00315 , H03K19/01721
摘要： A circuit generates complementary output signals which occur essentially simultaneously to each other. The circuit comprises three inverting and one non-inverting pairs of complementary transistors, typically field effect types. One of the inverting pairs provides the circuit inverted output. The output of the non-inverting pair is coupled to the output of another of the inverting pairs, which provide the circuit non-inverted output. In this manner, full Vss to Vcc output levels are achieved for substantially symmetrical output signals.
摘要翻译：电路产生基本上彼此同时发生的互补输出信号。该电路包括三个反相和一对互补晶体管，通常是场效应类型。其中一个反相对提供电路反相输出。非反相对的输出耦合到另一个反相对的输出端，提供电路非反相输出。以这种方式，对于基本对称的输出信号实现了完全Vss至Vcc的输出电平。

44. 发明授权

US4614885A Phase splitter with latch 失效
标题翻译：相分离器带闩锁
公开(公告)号：US4614885A
公开(公告)日：1986-09-30
申请号：US630544
申请日：1984-07-13
申请人： Rudolf Brosch , Joachim Keinert , Erich Klink , Friedrich C. Wernicke
发明人： Rudolf Brosch , Joachim Keinert , Erich Klink , Friedrich C. Wernicke
IPC分类号： H03K3/286 , H03K3/288 , H03K5/02 , H03K5/151 , H03K3/023
CPC分类号： H03K3/288
摘要： A phase splitter with latch comprises a true complement generator in the form of a current switch (T1, T2, T3, R3) which supplies two complementary output signals in response to an input signal (VIN). The outputs of this true complement generator are in each case connected to an associated emitter follower (T4, T5). The two emitter followers (T4, T5) have identical emitter resistors (R6, R7) which simultaneously serve as collector load resistors of two cross-coupled transistors (T6, T7) also comprise identical but higher emitter resistors (R13, R14) than the emitter followers (T6, T7). The emitters of the cross-coupled transistors (T6, T7) are each connected to one of the two inputs of an output stage (T8, T9, T11) consisting of a current switch. This current switch is connected to operating voltage (VEE) through a clock-controlled transistor (T11). Upon actuation of the output stage, i.e., when transistor (T11) is on, the active emitter resistance of one of the cross-coupled transistors (T6, T7) is pulled below the value of the emitter resistors (R6, R7) of the emitter followers (T4, T5), thus causing the latch circuit to be latched as a function of the input signal.
摘要翻译：具有锁存器的分相器包括形式为电流开关（T1，T2，T3，R3）形式的真互补发生器，其根据输入信号（VIN）提供两个互补输出信号。这种真互补发生器的输出在每种情况下都连接到相关的射极跟随器（T4，T5）。两个发射极跟随器（T4，T5）具有相同的发射极电阻（R6，R7），其同时用作两个交叉耦合晶体管（T6，T7）的集电极负载电阻，其也包括相同但较高的发射极电阻（R13，R14）发射极跟随器（T6，T7）。交叉耦合晶体管（T6，T7）的发射极各自连接到由电流开关组成的输出级（T8，T9，T11）的两个输入之一。该电流开关通过时钟控制的过渡器（T11）连接到工作电压（VEE）。在激励输出级时，即当晶体管（T11）导通时，其中一个交叉耦合晶体管（T6，T7）的有源发射极电阻被拉低到低于发射极电阻（R6，R7）的值发射极跟随器（T4，T5），从而使闩锁电路根据输入信号被锁存。

45. 发明授权

US4529896A True/complement generator employing feedback circuit means for controlling the switching of the outputs 失效
标题翻译：采用反馈电路的真/补生发生器用于控制输出的切换
公开(公告)号：US4529896A
公开(公告)日：1985-07-16
申请号：US448135
申请日：1982-12-09
申请人： Michel Grandguillot , Pierre Mollier , Jean-Paul Nuez
发明人： Michel Grandguillot , Pierre Mollier , Jean-Paul Nuez
IPC分类号： G11C11/413 , G11C8/06 , H03K5/151 , H03K5/15 , H03K19/088 , H03K19/20
CPC分类号： G11C8/06 , H03K5/1515
摘要： A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..
摘要翻译：用于产生加权地址位的补码和真值的真/补码发生器，防止地址解码器同时选择多个行。它包括两个电路（1）和（2），第一个提供真实值（phi），第二个提供其补码（phi）。在第一电路中，包括用于延迟（phi）的上升沿的晶体管（T11-1），只要它被电阻器R11-1和R10提供的电平保持在上，则防止发生多重选择的装置 -2从输出phi。第二回路中的晶体管T11-2只要保持在来自phi的R10-1，R11-2提供的电平，就能防止phi变高。

46. 发明授权

US4477738A LSSD Compatible clock driver 失效
标题翻译： LSSD兼容时钟驱动
公开(公告)号：US4477738A
公开(公告)日：1984-10-16
申请号：US387990
申请日：1982-06-14
申请人： Daniel J. Kouba
发明人： Daniel J. Kouba
IPC分类号： G01R31/28 , G01R31/3183 , H03K5/151 , H03K5/13 , G01R31/02
CPC分类号： H03K5/1515
摘要： A cross-coupled, latch-type clock driver circuit is disclosed which enables the carrying out of level sensitive scan design (LSSD) testing. During normal operation, the circuit functions to prevent a pair of input clock waveforms from overlapping. This is achieved by applying a low state to a control signal input which causes the circuit to perform a latching operation on the input clock waveforms by providing a conductive cross-coupled connection between a first and second NOR Logic elements connected to the input clock waveforms. Then the outputs of the NOR elements will be insured to be nonoverlapping. During the test mode, the input clock waveforms must not be latched, in order for LSSD testing to be carried out. This is achieved by applying a high state to the control signal input, which disables the cross-coupled connection between the NOR logic elements. The circuit then becomes transparent to the input clock waveforms, enabling testing operations to be performed. The transition of the circuit from its normal mode to its test mode is carried out with a staged delay operation to prevent inadvertent current surges.
摘要翻译：公开了一种交叉耦合的锁存型时钟驱动器电路，其能够执行电平敏感扫描设计（LSSD）测试。在正常操作期间，电路用于防止一对输入时钟波形重叠。这通过将低状态应用于控制信号输入来实现，该控制信号输入通过在连接到输入时钟波形的第一和第二NOR逻辑元件之间提供导电的交叉耦合连接来使得电路对输入时钟波形执行锁存操作。那么NOR元素的输出将被保险为非重叠。在测试模式下，输入时钟波形不能被锁存，以便进行LSSD测试。这通过将高状态应用于控制信号输入来实现，其控制NOR逻辑元件之间的交叉耦合连接。然后，电路对输入时钟波形变得透明，使得能够执行测试操作。电路从其正常模式转换到其测试模式是通过分阶段延迟操作进行的，以防止无意的电流浪涌。

47. 发明授权

US4472645A Clock circuit for generating non-overlapping pulses 失效
标题翻译：用于产生非重叠脉冲的时钟电路
公开(公告)号：US4472645A
公开(公告)日：1984-09-18
申请号：US333435
申请日：1981-12-22
申请人： Lincoln D. White
发明人： Lincoln D. White
IPC分类号： H03K5/151 , H03K3/356 , H03K5/153 , H03K17/284 , H03K17/693
CPC分类号： H03K5/1515
摘要： A clock generator for producing a two phase output comprises a bistable circuit having two stages. The output of each stage is cross coupled to the input of the other and each cross coupling path includes a high-resistance transfer gate. Each transfer gate forms part of an RC delay element which is so arranged that at a transition of clock signals the output of one of the stages completes its transition substantially at the same time as the output of the other stage begins its transition. This results in non-overlapping outputs from the generator.
摘要翻译：用于产生两相输出的时钟发生器包括具有两级的双稳态电路。每个级的输出交叉耦合到另一级的输入，并且每个交叉耦合路径包括高电阻传输门。每个传输门形成RC延迟元件的一部分，其被布置成使得在时钟信号的转变处，一个级的输出基本上在另一级的输出开始其转换的同时完成其转换。这导致来自发生器的不重叠的输出。

48. 发明授权

US4456837A Circuitry for generating non-overlapping pulse trains 失效
标题翻译：用于产生非重叠脉冲串的电路
公开(公告)号：US4456837A
公开(公告)日：1984-06-26
申请号：US311512
申请日：1981-10-15
申请人： Otto H. Schade, Jr.
发明人： Otto H. Schade, Jr.
IPC分类号： H03K5/151 , H03K5/00 , H03K5/01 , H03K5/156
CPC分类号： H03K5/1515
摘要： A two phase waveform generator for producing nonoverlapping pulses is designed with a CMOS inverter modified to include a resistor between the drain electrodes of the complementary inverter transistors and three conventional CMOS inverter circuits. The resistor n-type transistor interconnection exhibits a fast negative signal transition but a slower positive transition due to the resistor. This effect tends to shorten the duration of pulses applied to the inverter input. The shortened pulses are applied to a cascade connected pair of inverters to sharpen the waveform and produce a first phase output signal. The resistor-p-type transistor interconnection of the modified inverter exhibits a fast positive signal transition but a slower negative transition. This effect tends to widen pulses applied to the input. The widened pulses are applied to another inverter which complements the widened pulses ultimately generating narrower pulses which comprise a second phase signal. The first and second phase signals are antiphase with no pulse overlap.
摘要翻译：设计用于产生非重叠脉冲的两相波形发生器，其中CMOS反相器被修改为在互补逆变器晶体管的漏极和三个常规CMOS反相器电路之间包括电阻器。电阻器n型晶体管互连呈现快速的负信号转变，但由于电阻器而呈现较慢的正向跃迁。这种效应有可能缩短施加到逆变器输入端的脉冲的持续时间。将缩短的脉冲施加到级联的反相器对以锐化波形并产生第一相输出信号。修改后的反相器的电阻-P型晶体管互连呈现快速的正信号转变，但较慢的负转变。这种效应倾向于加宽施加到输入端的脉冲。加宽的脉冲被施加到另一个逆变器，该逆变器补充加宽的脉冲，最终产生包括第二相位信号的较窄脉冲。第一和第二相信号为反相，无脉冲重叠。

49. 发明授权

US4209715A Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US4209715A
公开(公告)日：1980-06-24
申请号：US859139
申请日：1977-12-09
申请人： Kiyoshi Aoki
发明人： Kiyoshi Aoki
IPC分类号： H03K3/037 , H03K3/286 , H03K3/288 , H03K3/72 , H03K5/151 , H03K19/00 , H03K19/08 , H03K19/082 , H03K19/091 , H03K23/00 , H03K23/52 , H03K23/58 , H03K19/20 , H03K21/00
CPC分类号： H03K19/08 , H03K3/0372 , H03K3/286 , H03K3/288 , H03K3/72
摘要： A logic circuit comprises four NAND or NOR gates. The first and second gates are cross-coupled and the third and fourth gates are also cross-coupled. The outputs of the first and second gates are coupled to the inputs of the third and fourth gates respectively. Complementary clock pulses are respectively supplied to the first and second gates and the third and fourth gates, and first and second logic inputs are applied to the inputs of the first and second gates, respectively.
摘要翻译：逻辑电路包括四个NAND或NOR门。第一和第二栅极是交叉耦合的，第三和第四栅极也是交叉耦合的。第一和第二栅极的输出分别耦合到第三和第四栅极的输入端。互补时钟脉冲分别提供给第一和第二栅极以及第三和第四栅极，并且第一和第二逻辑输入分别被施加到第一和第二栅极的输入端。

50. 发明授权

US4157580A Fail-safe time delay circuit 失效
标题翻译：故障安全延时电路
公开(公告)号：US4157580A
公开(公告)日：1979-06-05
申请号：US874007
申请日：1978-01-31
申请人： John H. Auer, Jr. , David B. Rutherford, Jr.
发明人： John H. Auer, Jr. , David B. Rutherford, Jr.
IPC分类号： H01H47/00 , H01H47/04 , H01H47/18 , H03K5/15 , H03K5/151
CPC分类号： H03K5/15 , H01H47/002 , H03K5/151 , H03K5/1515 , H01H47/043 , H01H47/18
摘要： A fail-safe time delay circuit is provided to produce an output a predetermined time, and no less than a predetermined time after an input stimulus. The circuit includes a driving circuit for a pair of relays which are operated at slightly greater than 50% duty cycle and out of phase such that, except when the circuit is de-energized, at least one of the relays is always energized. The contacts of the two relays are employed in a balanced voltage amplifier to produce a bi-polar signal, with the magnitude of both polarities increasing, with the time required for the increase to a defined threshold establishing the time delay. A pair of threshold circuits are coupled to the output of the balanced voltage amplifier such that each threshold circuit (one responding to the positive portion, and the other the negative portion of the bi-polar output) is energized when the respective portion of the bi-polar signal is detected to reach the associated threshold. Each of the threshold circuits provides an input to a vital AND gate such that only when the excursion in the bi-polar signal exceeds the threshold of both threshold circuits will the vital AND gate produce an output to energize a load.
摘要翻译：提供故障安全时间延迟电路以在输入刺激之后不小于预定时间产生预定时间的输出。电路包括用于一对继电器的驱动电路，其以略大于50％的占空比和异相操作，使得除了当电路断电时，至少一个继电器总是通电。两个继电器的触点用于平衡电压放大器中以产生双极性信号，两极性的大小随着增加到确定时间延迟的确定阈值所需的时间而增加。一对阈值电路耦合到平衡电压放大器的输出端，使得每个阈值电路（一个响应于正极部分，另一个是双极输出的负极部分）被激励，当Bi 检测到极性信号以达到相关阈值。每个阈值电路向重要的与门提供输入，使得只有当双极信号中的偏移超过两个阈值电路的阈值时，重要的“与”门才会产生一个输出以激励负载。

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