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1. 发明申请

US20180302037A1 LOW POWER TIME AMPLIFIER AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20180302037A1
公开(公告)日：2018-10-18
申请号：US15926951
申请日：2018-03-20
申请人： Gwangju Institute of Science and Technology
发明人： Min Jae LEE , Min Uk HEO
IPC分类号： H03F1/02
CPC分类号： H03F1/0211 , H03K3/356182 , H03K5/01 , H03K5/15006
摘要： A time amplifier includes a first signal regeneration circuit, a second signal regeneration circuit, a first delay circuit configured to receive the second input signal and output the delayed second input signal by a predetermined delay time, and a second delay circuit configured to receive the first input signal and output the delayed first input signal by the predetermined delay time. A corresponding signal regeneration operation is stopped when at least one of the first and second output signals is high. The at least one output signal remains high.

2. 发明授权

US08912836B1 Low power quadrature waveform generator 有权
标题翻译：低功率正交波形发生器
公开(公告)号：US08912836B1
公开(公告)日：2014-12-16
申请号：US13952767
申请日：2013-07-29
申请人： Futurewei Technologies, Inc.
发明人： Lawrence E. Connell , Daniel P. McCarthy , Brian T. Creed
IPC分类号： H03H11/16 , H03H11/22
CPC分类号： H03K5/15006
摘要： An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.
摘要翻译：一种包括分频器的装置，包括：第一锁存器，被配置为接收第一时钟信号和第一时钟信号的补码，并产生第一锁存器第一输出;以及第二锁存器，以触发器配置耦合到第一锁存器，包括p沟道晶体管的第一输出电路，其中p沟道晶体管的栅极被配置为接收第一时钟信号，以及n沟道晶体管，其中p沟道晶体管的漏极直接连接到 n沟道晶体管的漏极，其中n沟道晶体管的栅极被配置为接收第一锁存器第一输出，其中n沟道晶体管的源被配置为接收第一时钟信号的补码，并且其中第一输出电路被配置为产生同相参考信号，以及第二输出电路，被配置为产生正交信号。

3. 发明授权

US6055287A Phase-comparator-less delay locked loop 失效
标题翻译：相位比较器延迟锁定环路
公开(公告)号：US6055287A
公开(公告)日：2000-04-25
申请号：US84541
申请日：1998-05-26
申请人： Thomas E. McEwan
发明人： Thomas E. McEwan
IPC分类号： G06F1/06 , G01S7/282 , G01S13/18 , G01S13/28 , H03K5/15 , H03L7/081 , H03L7/097 , H04L7/033 , H03L7/06
CPC分类号： G01S13/18 , G01S13/28 , H03K5/15006 , H03L7/0812 , H03L7/097
摘要： A delay locked loop clock circuit employs an analog control loop for generating picosecond-accurate clock delays. A linear analog comparison circuit operating on integrated DC levels replaces the usual digital phase comparator for substantially improved timing accuracy. In operation, clock pulses from a first delay path are integrated and applied to a loop control amplifier. Clock pulses from a second delay path are integrated and applied to a differencing input of the loop control amplifier. The loop control amplifier regulates the delay in the second delay path to balance the integrated clock pulse voltages against externally applied control voltages. The delay between the first path and the second path is thereby precisely controlled by external voltage inputs. The first and second path clock output timing relationship is directly measured by analog voltage devices, eliminating error-prone high-speed phase comparators employed in prior art approaches.
摘要翻译：延迟锁定环时钟电路采用模拟控制环来产生微秒级精确的时钟延迟。在集成直流电平上工作的线性模拟比较电路取代了通常的数字相位比较器，以显着提高定时精度。在操作中，来自第一延迟路径的时钟脉冲被积分并且被施加到环路控制放大器。来自第二延迟路径的时钟脉冲被积分并且被施加到环路控制放大器的差分输入。环路控制放大器调节第二延迟路径中的延迟，以平衡集成时钟脉冲电压与外部施加的控制电压。因此，第一路径和第二路径之间的延迟由外部电压输入精确地控制。第一和第二路径时钟输出定时关系由模拟电压装置直接测量，消除了现有技术方法中使用的容易出错的高速相位比较器。

4. 发明授权

US3798538A Pulse eddy current testing apparatus with ramp phase shifter 失效
标题翻译：脉冲EDDY电流测试装置与相位移相器
公开(公告)号：US3798538A
公开(公告)日：1974-03-19
申请号：US3798538D
申请日：1973-02-22
申请人： MAGNETIC ANALYSIS CORP
发明人： MANSSON S
IPC分类号： G01N27/90 , H03K5/04 , H03K5/15 , G01N27/86
CPC分类号： G01N27/9046 , H03K5/04 , H03K5/15006
摘要： Time adjustable pairs of gate pulses for gating phase-sensitive detectors in pulse eddy current testing apparatus are produced by a ramp generator responsive to pulses corresponding to the driving pulses applied to the test coil assembly, an adjustable level control circuit for changing the DC level of the ramps, a pair of electronic switching circuits which switch at different instantaneous values of the ramps, and means responsive to the switching for producing pairs of gate pulses. The pairs of gate pulses may be quadrature-related and their time occurrence shifted with respect to the driving pulses by changing the ramp level. An adjustable clamping circuit for level control, a pair of switching amplifiers, and differentiating the outputs of the switching amplifiers to produce the gate pulses are specifically described.
摘要翻译：用于脉冲涡流测试装置中门控相敏检测器的时间可调对门脉冲是由响应于施加到测试线圈组件的驱动脉冲的脉冲的斜坡发生器产生的，可调节电平控制电路用于改变斜坡，一对在斜坡的不同瞬时值切换的电子切换电路，以及响应于切换以产生一对门脉冲的装置。栅极脉冲对可以是正交相关的，并且它们的时间出现相对于驱动脉冲通过改变斜坡电平而偏移。具体描述用于电平控制的可调钳位电路，一对开关放大器以及微分开关放大器的输出以产生栅极脉冲。

5. 发明授权

US11831318B1 Frequency multiplier system with multi-transition controller 有权
公开(公告)号：US11831318B1
公开(公告)日：2023-11-28
申请号：US17989475
申请日：2022-11-17
申请人： Movellus Circuits Incorporated
发明人： Scott Howe , Xiao Wu , Jeffrey Alan Fredenburg
IPC分类号： H03K21/00 , H03K5/00 , H03K21/02 , H03K5/15 , H03K21/12
CPC分类号： H03K5/00006 , H03K5/15006 , H03K21/02 , H03K21/12
摘要： A frequency multiplier system includes a first frequency multiplier circuit to generate a first signal having a first frequency. The first frequency multiplier circuit includes a first post-divider circuit to divide the first frequency of the first signal to a first output frequency within a bounded first range of frequencies, and a first programmable frequency transition controller to control a transitioning frequency relationship between the first signal having the first frequency and a target signal having a desired target frequency. The system includes a second frequency multiplier circuit to generate a second signal having a second frequency. The second frequency multiplier circuit includes a second post-divider circuit configured to divide the second frequency of the second signal to a second output frequency within a bounded second range of frequencies, and a second programmable frequency transition controller to control a transitioning frequency relationship between the second signal having the second frequency and the target signal having the desired target frequency. A multi-transition controller is coupled to both the first frequency multiplier circuit and the second frequency multiplier circuit to, upon a desired change from the first output frequency to the target output frequency, select one of the first output frequency or the second output frequency as a system output frequency.

6. 发明授权

US09608612B2 Time amplifier and method for controlling the same 有权
公开(公告)号：US09608612B2
公开(公告)日：2017-03-28
申请号：US14257031
申请日：2014-04-21
申请人： Industry-Academic Cooperation Foundation, Yonsei University
发明人： Doohyun Shon , Yeomyung Kim , Tae Wook Kim
IPC分类号： G06G7/12 , H03K5/15
CPC分类号： H03K5/15006
摘要： Provided is a time amplifier. The time amplifier includes: an SR latch providing an output at a timing determined according to a time difference between two inputs; and an operation determination unit connected to a power terminal of the SR latch and configured to determine an operation of the SR latch.

7. 发明申请

US20160182029A1 STROBE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME 有权
标题翻译：使用相同的步进信号发生电路和半导体装置
公开(公告)号：US20160182029A1
公开(公告)日：2016-06-23
申请号：US14634314
申请日：2015-02-27
申请人： SK hynix Inc.
发明人： Jin Hwan KIM , Young Jun KU
IPC分类号： H03K5/15 , G11C7/22
CPC分类号： H03K5/15006 , G11C7/222
摘要： A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal.
摘要翻译：选通信号生成电路可以包括：计数器，用于通过对外部选通信号进行计数来产生第一源信号和第二源信号; 通过将第一源信号和第二源信号延迟预设时间来产生第一延迟信号和第二延迟信号的延迟; 以及组合单元，通过选择性地组合第一源信号，第二源信号，第一延迟信号和第二延迟信号来产生内部选通信号。

8. 发明授权

US08928369B1 Low power local oscillator quadrature generator 有权
标题翻译：低功率本地振荡器正交发生器
公开(公告)号：US08928369B1
公开(公告)日：2015-01-06
申请号：US13955197
申请日：2013-07-31
申请人： Futurewei Technologies, Inc.
发明人： Kent Jaeger , Lawrence E. Connell , Daniel P. McCarthy , Brian T. Creed
IPC分类号： H03K21/10 , H03B19/00 , H03K3/353
CPC分类号： H03K5/15006
摘要： An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.
摘要翻译：一种包括分频器的装置，包括以触发器配置耦合到第一锁存器的第一锁存器和第二锁存器，以及包括第一p沟道晶体管的输出电路，其中第一p沟道晶体管的栅极被配置以接收时钟信号，第一n沟道晶体管，其中所述第一n沟道晶体管的栅极耦合到所述第一锁存器，与所述第一p沟道晶体管串联连接的第二n沟道晶体管和所述第一n沟道晶体管，并且其中所述第二n沟道晶体管的栅极被配置为接收所述时钟信号;第二p沟道晶体管，其中所述第二p沟道晶体管的栅极被配置为接收所述时钟信号;以及第三p沟道晶体管， n沟道晶体管与第二p沟道晶体管和第二n沟道晶体管串联，其中输出电路被配置为产生一对同相参考信号。

9. 发明授权

US08207762B2 Digital time base generator and method for providing a first clock signal and a second clock signal 有权
标题翻译：数字时基发生器和用于提供第一时钟信号和第二时钟信号的方法
公开(公告)号：US08207762B2
公开(公告)日：2012-06-26
申请号：US12683194
申请日：2010-01-06
申请人： George Burcea
发明人： George Burcea
IPC分类号： H03K21/00
CPC分类号： G01S7/288 , H03K5/15006 , H03L7/23
摘要： A digital time base generator and method for providing a first clock signal and a second clock signal in which a base clock signal having a base frequency is generated to provide two clock signals of slightly different frequencies with defined time or phase delay. Here, the base frequency is divided by a first integer to produce a first auxiliary signal, the frequency of the first auxiliary signal is multiplied by a factor to obtain the first clock signal, the base frequency is further divided by a second integer to produce a second auxiliary signal, and the frequency of the second auxiliary signal is multiplied by the factor to obtain the second clock signal.
摘要翻译：一种用于提供第一时钟信号和第二时钟信号的数字时基发生器和方法，其中产生具有基频的基本时钟信号以提供具有限定的时间或相位延迟的稍微不同频率的两个时钟信号。这里，将基本频率除以第一整数以产生第一辅助信号，将第一辅助信号的频率乘以因子以获得第一时钟信号，将基频进一步除以第二整数，以产生第二辅助信号，并且第二辅助信号的频率乘以因子以获得第二时钟信号。

10. 发明授权

US4399410A Circuit for generating two periodic signals having a controllable phase relationship therebetween 失效
标题翻译：用于产生其间具有可控相位关系的两个周期信号的电路
公开(公告)号：US4399410A
公开(公告)日：1983-08-16
申请号：US291455
申请日：1981-08-10
申请人： Gary G. Siegmund , Robert J. Kretschmann
发明人： Gary G. Siegmund , Robert J. Kretschmann
IPC分类号： H03K5/15 , H03K5/151 , H03K5/153
CPC分类号： H03K5/15006 , H03K5/151
摘要： A circuit for generating at least two periodic output signals having a phase relationship controllable between zero and 180 degrees as a function of a d.c. control signal as compared to a ramp signal. Also included is circuitry for controlling the phase relationship to be at substantially 180 degrees when the d.c. control signal is always greater than the ramp signal and to be at substantially zero degrees when the d.c. control signal is always less than the ramp signal.
摘要翻译：用于产生至少两个周期性输出信号的电路，其具有在0和180度之间可控的相位关系，作为直流的函数。控制信号与斜坡信号相比。还包括用于将相位关系控制在大致180度的电路。控制信号总是大于斜坡信号，并且当直流电平时基本为零度。控制信号始终小于斜坡信号。

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