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1. 发明授权

US4617477A Symmetrical output complementary buffer 失效
标题翻译：对称输出互补缓冲器
公开(公告)号：US4617477A
公开(公告)日：1986-10-14
申请号：US736554
申请日：1985-05-21
申请人： Michael V. DePaolis, Jr.
发明人： Michael V. DePaolis, Jr.
IPC分类号： H03K19/0948 , H03K5/151 , H03K19/003 , H03K19/017 , H03K19/094 , H03K3/86 , H03K17/693 , H03K19/20
CPC分类号： H03K5/151 , H03K19/00315 , H03K19/01721
摘要： A circuit generates complementary output signals which occur essentially simultaneously to each other. The circuit comprises three inverting and one non-inverting pairs of complementary transistors, typically field effect types. One of the inverting pairs provides the circuit inverted output. The output of the non-inverting pair is coupled to the output of another of the inverting pairs, which provide the circuit non-inverted output. In this manner, full Vss to Vcc output levels are achieved for substantially symmetrical output signals.
摘要翻译：电路产生基本上彼此同时发生的互补输出信号。该电路包括三个反相和一对互补晶体管，通常是场效应类型。其中一个反相对提供电路反相输出。非反相对的输出耦合到另一个反相对的输出端，提供电路非反相输出。以这种方式，对于基本对称的输出信号实现了完全Vss至Vcc的输出电平。

2. 发明授权

US5917769A Method and system rotating data in a memory array device 失效
标题翻译：在存储器阵列器件中的方法和系统旋转数据
公开(公告)号：US5917769A
公开(公告)日：1999-06-29
申请号：US909866
申请日：1997-08-12
申请人： Michael V. DePaolis, Jr.
发明人： Michael V. DePaolis, Jr.
IPC分类号： G11C8/12 , G11C8/16 , G11C7/00
CPC分类号： G11C8/12 , G11C8/16
摘要： A method and system of utilizing a memory array device contained within an integrated circuit within the printer device is provided in which data bits are written in a row format, thereby filling an N.times.M memory array device and then read in a column format. An N.times.M memory array device is employed such as a 32.times.32 bit memory array. During the reading phase, data from a computer is read by the memory device in a parallel fashion so that data is written sequentially a row of memory cells, such as B0W0, B1W0, B2W0 . . . etc. Once the memory array is loaded up, the writing phase is accomplished by performing a parallel dump wherein all of the memory cells of the first column are read together such that a column of memory cells, such as B0W0 to B0W31 is read first, a column of memory cells, such as B1W0 to B1W31 is read second, a column of memory cells B2W0 to B2W31 is read third etc. The N.times.M memory array device is read in a column format instead of the standard row format. As is evident, one or more arrays may be utilized.
摘要翻译：提供了利用包含在打印机设备内的集成电路内的存储器阵列器件的方法和系统，其中以行格式写入数据位，从而填充NxM存储器阵列器件，然后以列格式读取。使用NxM存储器阵列器件，例如32×32位存储器阵列。在读取阶段期间，存储器件以并行方式读取来自计算机的数据，使得数据顺序地写入一行诸如B0W0，B1W0，B2W0的存储器单元。。。一旦存储器阵列被加载，写入阶段通过执行并行转储来完成，其中第一列的所有存储单元被一起读出，使得诸如B0W0到B0W31的存储单元列首先被读取，读取第一列存储单元（例如B1W0至B1W31），一列存储单元B2W0至B2W31被读取第三等。以列格式而不是标准行格式读取N×M存储器阵列器件。显然，可以使用一个或多个阵列。

3. 发明授权

US4590388A CMOS spare decoder circuit 失效
标题翻译： CMOS备用解码电路
公开(公告)号：US4590388A
公开(公告)日：1986-05-20
申请号：US602680
申请日：1984-04-23
申请人： Donald G. Clemons , Michael V. DePaolis, Jr.
发明人： Donald G. Clemons , Michael V. DePaolis, Jr.
IPC分类号： G11C29/00 , H03K19/096 , G11C7/00 , H03K19/003 , H03K19/20
CPC分类号： G11C29/83
摘要： A spare decoder provides for the substitution of a spare component for repair of a defective semiconductor chip. For example, a spare row or column of memory cells can be substituted for a defective row or column of a memory chip by fusing fusible links in the decoder. The present invention implements the decoder in CMOS technology. To minimize power consumption, means are included for preventing current flow in an unused spare without having to fuse a link.
摘要翻译：备用解码器提供替换备件以修复缺陷半导体芯片。例如，通过将解码器中的可熔链路融合，可以将存储器单元的备用行或列替代存储器芯片的有缺陷的行或列。本发明实现了CMOS技术中的解码器。为了最小化功率消耗，包括用于防止未使用的备用电流的流动，而不必熔断链路。

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