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41. 发明授权

US06632372B1 Method of forming via-holes in multilayer circuit boards 失效
标题翻译：在多层电路板中形成通孔的方法
公开(公告)号：US06632372B1
公开(公告)日：2003-10-14
申请号：US09717081
申请日：2000-11-22
申请人： Man-Lin Chen , Hsien-Kuang Lin , Chuang-Shin Chiou , Tien-Shou Shieh , Pey-Ching Liou
发明人： Man-Lin Chen , Hsien-Kuang Lin , Chuang-Shin Chiou , Tien-Shou Shieh , Pey-Ching Liou
IPC分类号： H01B1300
CPC分类号： H05K3/0017 , H05K3/4602 , H05K2203/025 , H05K2203/0582
摘要： The invention discloses a method of forming via-holes in multilayer circuit boards. The process includes forming covering substances in predetermined spots in a multilayer circuit board and thereafter applying an insulating layer upon the circuit board. The predetermined spots are then uncovered and the covering substances are removed to form via-holes.
摘要翻译：本发明公开了一种在多层电路板中形成通孔的方法。该方法包括在多层电路板中的预定点形成覆盖物质，然后在电路板上施加绝缘层。然后将预定的点未被覆盖，并且去除覆盖物质以形成通孔

42. 发明授权

US06602431B2 Enhancements in sheet processing and lead formation 失效
公开(公告)号：US06602431B2
公开(公告)日：2003-08-05
申请号：US10295273
申请日：2002-11-15
申请人： Konstantine Karavakis
发明人： Konstantine Karavakis
IPC分类号： H01B1300
CPC分类号： H01L23/49827 , H01L23/49811 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A connection component for making microelectronic assemblies includes a dielectric structural layer having a first surface and a plurality of conductive leads having first and second ends overlying the first surface of the dielectric structural layer. An adhesive is provided between the second ends of the leads and the dielectric structural layer such that the adhesive forms connections between the second ends of the leads and the structural layer. The formed connections have areas smaller than the areas of the second ends. The second ends of the leads are releasably attached to the structural layer by the connections. Thus, the second ends of the leads may be engaged with features on a microelectronic device and the microelectronic elements may be moved away from the structural layer so as to bend the second ends of the leads away from the structural layer.

43. 发明授权

US06585904B2 Method for the manufacture of printed circuit boards with plated resistors 有权
公开(公告)号：US06585904B2
公开(公告)日：2003-07-01
申请号：US09784242
申请日：2001-02-15
申请人： Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
发明人： Peter Kukanskis , Dennis Fritz , Frank Durso , Steven Castaldi , David Sawoska
IPC分类号： H01B1300
CPC分类号： H01C17/24 , H01C17/242 , H05K1/167 , H05K3/027 , H05K3/064 , H05K3/184 , H05K2201/0344 , H05K2203/0315 , H05K2203/107 , H05K2203/1105 , H05K2203/1453 , H05K2203/171
摘要： A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.

44. 发明授权

US06582616B2 Method for preparing ball grid array board 失效
公开(公告)号：US06582616B2
公开(公告)日：2003-06-24
申请号：US09984284
申请日：2001-10-29
申请人： Myung-Sam Kang , Keon-Yang Park , Won-Hoe Kim
发明人： Myung-Sam Kang , Keon-Yang Park , Won-Hoe Kim
IPC分类号： H01B1300
CPC分类号： H01L21/4803 , H01L21/4857 , H01L23/13 , H01L23/49833 , H01L2924/0002 , H05K3/4611 , Y10T29/49155 , Y10T29/49169 , H01L2924/00
摘要： Disclosed are a method for preparing a high performance BGA board containing a plurality of printed circuit boards in which a conductor circuit, a bonding pad electrically connected to a semiconductor chip, and an inner hole for mounting a semiconductor chip are formed, by primary- and secondary-laminating a plurality of boards. The present invention enjoys advantages in that contamination due to an outer layer surface treatment of the board laminate can be prevented, and a process for preventing a contamination of an inner hole can be omitted, and also a defective proportion can be reduced remarkably in comparison with prior arts by applying a pressure uniformly during a secondary lamination. Furthermore, a BGA board according to the invention has an ideal ball pitch and multi-fins, excellent electrical and thermal properties, also can be applied in the case of high current, and can be easily mounted on a chip.

45. 发明授权

US06547974B1 Method of producing fine-line circuit boards using chemical polishing 失效
标题翻译：使用化学抛光生产细线电路板的方法
公开(公告)号：US06547974B1
公开(公告)日：2003-04-15
申请号：US08495277
申请日：1995-06-27
申请人： Stanley Michael Albrechta , Christina Marie Boyko , Kathleen Lorraine Covert , Natalie Barbara Feilchenfeld , Voya Rista Markovich , William Earl Wilson , Michael Wozniak
发明人： Stanley Michael Albrechta , Christina Marie Boyko , Kathleen Lorraine Covert , Natalie Barbara Feilchenfeld , Voya Rista Markovich , William Earl Wilson , Michael Wozniak
IPC分类号： H01B1300
CPC分类号： H05K3/22 , H05K3/06 , H05K3/062 , H05K3/108 , H05K2203/025 , H05K2203/0346 , H05K2203/0353 , H05K2203/0392 , H05K2203/1476
摘要： A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material. The removal step is repeated until the conductive material is at a desired height relative to the height of the resist layer. The board is then finished using conventional circuit board fabrication techniques.
摘要翻译：通过根据限定所需电路路径的电路掩模图案化抗蚀剂层来制造印刷电路板。抗蚀剂图案层通过在所需的电路路径中从基板上去除抗蚀剂而形成，并且导电材料被电镀在由电路掩模限定的抗蚀剂空隙中的基板上，使得导电材料相对于基板的高度等于或等于超过抗蚀剂层相对于基底的高度。将低反应性溶液施加在导电材料上并除去导电材料的表面部分。当溶液去除导电层时，其形成膜阻挡层并且溶液组成发生变化，这两者基本上禁止任何进一步去除导电材料。接下来，从板上去除膜屏障，允许另一个膜屏障形成刺激去除另外的导电材料。重复去除步骤，直到导电材料相对于抗蚀剂层的高度处于期望的高度。然后使用常规电路板制造技术完成电路板。

46. 发明授权

US06531067B1 Method for forming contact hole 有权
标题翻译：形成接触孔的方法
公开(公告)号：US06531067B1
公开(公告)日：2003-03-11
申请号：US09623026
申请日：2000-08-25
申请人： Nagamasa Shiokawa , Atsushi Yamamoto
发明人： Nagamasa Shiokawa , Atsushi Yamamoto
IPC分类号： H01B1300
CPC分类号： H01L21/31116 , H01L21/76802
摘要： The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level interconnect structure in which at least the lower wiring layer is an aluminum wiring layer. Contact holes (31, 51) are formed in dielectric interlayers (3, 5) of upper and lower wiring layers (1, 2, 4) by dry etching. In the method of forming the contact holes of the invention, the dry etching was applied in two steps divisionally. The first step of etching is applied with supplying CF4, CHF3, Ar and N2 into an etching chamber. The second step of etching is conducted with supplying CF4, CHF3 and Ar into the etching gas chamber.
摘要翻译：本发明的目的在于使至少下布线层为铝布线层的多层布线结构的半导体器件中的同一批次中的布线电阻变小，从而降低布线电阻的变化。接触孔（31,51）通过干蚀刻形成在上下布线层（1,2,4）的介电层间（3,5）中。在形成本发明的接触孔的方法中，分两次地进行干蚀刻。施加蚀刻的第一步骤，将CF4，CHF3，Ar和N2供应到蚀刻室中。蚀刻第二步骤是通过向蚀刻气体室中供应CF4，CHF3和Ar进行蚀刻。

47. 发明授权

US06501024B1 Termination for electrical cable 有权
标题翻译：电缆端接
公开(公告)号：US06501024B1
公开(公告)日：2002-12-31
申请号：US09869829
申请日：2001-10-05
申请人： Ian Richard Evans
发明人： Ian Richard Evans
IPC分类号： H01B1300
CPC分类号： H02G15/068 , H02G15/003 , H02G15/06
摘要： A termination for an electrical power cable includes a load carrying conductor, the termination including an insulating outer member through which the load carrying conductor, or an extension of it, runs substantially longitudinally, and means for controlling electrical stress concentrations within the outer member. Residual space within the outer member is occupied by electrically insulating solid granules. Interstices between the granules are filled with electrically insulating fluid.
摘要翻译：电力电缆的终端包括负载承载导体，该终端包括绝缘外部构件，负载承载导体或其延伸部基本上纵向延伸，以及用于控制外部构件内的电应力集中的装置。外部构件内的残余空间由电绝缘固体颗粒占据。颗粒之间的间隙填充有电绝缘流体。

48. 发明授权

US06402970B1 Method of making a support circuit for a semiconductor chip assembly 失效
标题翻译：制造用于半导体芯片组件的支撑电路的方法
公开(公告)号：US06402970B1
公开(公告)日：2002-06-11
申请号：US09643213
申请日：2000-08-22
申请人： Charles W. C. Lin
发明人： Charles W. C. Lin
IPC分类号： H01B1300
CPC分类号： H05K3/4007 , H01L21/4857 , H01L23/49811 , H01L23/4985 , H01L2924/0002 , H01L2924/09701 , H05K3/062 , Y10S205/92 , Y10T29/49128 , Y10T29/49156 , H01L2924/00
摘要： A method of manufacturing a support circuit includes providing a conductive layer with top and bottom surfaces, providing a top etch mask on the top surface that includes an opening that exposes a portion of the top surface, providing a bottom etch mask on the bottom surface that includes an opening that exposes a portion of the bottom surface, applying an etch to the exposed portion of the top surface through the opening in the top etch mask, thereby etching partially but not completely through the conductive layer and forming a recessed portion in the conductive layer below the top surface, forming an insulative base on the recessed portion without forming the insulative base on the top surface, and applying an etch to the exposed portion of the bottom surface through the opening in the bottom etch mask, thereby forming a through-hole in the recessed portion that extends to and is covered by the insulative base.
摘要翻译：制造支撑电路的方法包括：提供具有顶表面和底表面的导电层，在顶表面上提供顶部蚀刻掩模，该掩模包括暴露顶表面的一部分的开口，在底表面上提供底蚀刻掩模，包括露出底表面的一部分的开口，通过顶部蚀刻掩模中的开口对顶表面的暴露部分施加蚀刻，从而通过导电层部分蚀刻但不完全蚀刻，并在导电层中形成凹陷部分在顶表面下方形成绝缘基底，而不在顶表面上形成绝缘基底，并且通过底蚀刻掩模中的开口对底表面的暴露部分施加蚀刻，从而形成通孔，在凹部中延伸并被绝缘基底覆盖的孔。

49. 发明授权

US06296725B1 High frequency ribbon cable for twist capsule cable applications 失效
标题翻译：用于扭转胶囊电缆应用的高频带状电缆
公开(公告)号：US06296725B1
公开(公告)日：2001-10-02
申请号：US09398017
申请日：1999-09-17
申请人： Glenn Lawson , Tyrone Trenor , Anthony Lee Bowman
发明人： Glenn Lawson , Tyrone Trenor , Anthony Lee Bowman
IPC分类号： H01B1300
CPC分类号： H01B13/22
摘要： Disclosed is a method for surrounding electrical cable, such as coax cable or twinax cable, with an elastomer to form a twist capsule cable. The cables are placed in a fixture and stretched to a desired tautness using rubber bands at opposite ends of each cable without allowing the cables to sag in the fixture. The cables are clamped into yokes at opposite ends of the fixture. An elastomer, such as silicone, is poured into the fixture and allowed to cure. The portion of the cables within the fixture are embedded into the elastomer after the elastomer cures. Additional length of twist capsule cable can be fabricated by performing a similar process on adjoining sections of cable. The elastomer is then coated with a polyxylylene or similar polymer such as Parylene™ to prevent the elastomer from rubbing on itself when coiled and when uncoiling. Advantageously, any number of cables can be embedded in the elastomer to form the twist capsule cable. Also advantageously, the present invention provides excellent attenuation at 1 GHz. Some channels operate between 10 MHz and 80 MHz. The cables are capable of carrying radio, Identify Friend and Foe (IFF), Ethernet and other signals.
摘要翻译：公开了一种用弹性体围绕诸如同轴电缆或双轴电缆的电缆的方法，以形成扭转胶囊电缆。将电缆放置在固定装置中，并使用每根电缆两端的橡胶带将其拉伸至所需的张紧状态，而不允许电缆在固定装置中下垂。电缆在夹具的相对端被夹紧到轭中。将诸如硅氧烷的弹性体倒入夹具中并使其固化。在弹性体固化之后，固定装置内的电缆部分被嵌入到弹性体中。扭绞胶囊电缆的附加长度可以通过在电缆的相邻部分上执行类似的工艺来制造。然后用聚亚苯基或类似聚合物如Parylene TM涂覆弹性体，以防止弹性体在卷绕时和当开卷时自身摩擦。有利地，可以将任何数量的电缆嵌入到弹性体中以形成扭转胶囊电缆。还有利地，本发明在1GHz提供了优异的衰减。一些通道在10 MHz和80 MHz之间运行。电缆能够携带无线电，识别朋友和敌人（IFF），以太网和其他信号。

50. 发明授权

US06280640B1 Process for manufacturing a chip carrier substrate 有权
标题翻译：芯片载体基板的制造方法
公开(公告)号：US06280640B1
公开(公告)日：2001-08-28
申请号：US09303422
申请日：1999-05-03
申请人： Dror Hurwitz , Boris Yofis , Dror Katz , Eva Igner
发明人： Dror Hurwitz , Boris Yofis , Dror Katz , Eva Igner
IPC分类号： H01B1300
CPC分类号： H05K3/4647 , H01L21/4846 , H01L21/4857 , H01L23/498 , H01L23/49822 , H01L2924/0002 , H01L2924/3011 , H05K2203/0315 , H05K2203/1142 , H01L2924/00
摘要： A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.
摘要翻译：一种制造芯片载体衬底的方法，该方法包括以下步骤：在衬底上提供第一铜导体层，在第一层铜导体上形成第一层阻挡金属层，在第一层上形成一层铝层的阻挡金属，在铝层上形成第二阻挡金属，将顶部阻挡金属图案化成螺柱形式，阳极氧化未被顶部阻挡金属保护的铝，去除氧化铝并图案化第一铜层，去除所有暴露的阻隔金属; 用聚合物电介质围绕螺栓和铜导体; 抛光聚合物电介质以暴露螺柱; 以及在所述平面聚合物电介质上形成第二层铜导体。

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