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41. 发明授权

US07092393B1 Method and apparatus for distributed reassembly of subdivided packets using multiple reassembly components 有权
标题翻译：用于使用多个重组组件分布式重新组装细分包的方法和装置
公开(公告)号：US07092393B1
公开(公告)日：2006-08-15
申请号：US09777095
申请日：2001-02-04
申请人： Gregg Anthony Westbrook , Thomas Dejanovic
发明人： Gregg Anthony Westbrook , Thomas Dejanovic
IPC分类号： H04L12/56
CPC分类号： H04L49/608 , H04L49/15 , H04L49/3072 , H04L49/552 , H04L2012/5652
摘要： Methods and apparatus are disclosed for distributed reassembly of large packets split into smaller packets. Larger packets are split into several smaller packets, which are marked with a sequence number, timestamp, or other ordering and reassembly indications, and sent through a system or network. These smaller packets are received at the destination location by multiple reassembly components, which distribute information as to received packets and coordinate the sending of packets from themselves so as to produce the reassembled larger packets. In one implementation, each of the multiple reassembly components maintains one or more data structures indicating packets stored locally and those packets stored anywhere or elsewhere within the multiple reassembly components. When all smaller packets comprising a larger packet are received by one of the distributed resequencing components, the reassembly components transmit their smaller packets in a coordinated fashion as to produce the original larger packet.
摘要翻译：公开了用于分组重新分组成较小分组的大分组的方法和装置。更大的数据包被分成几个更小的数据包，它们被标记为序列号，时间戳或其他排序和重组指示，并通过系统或网络发送。这些较小的数据包通过多个重组组件在目的位置被接收，多个重组组件分配关于接收到的分组的信息，并协调来自它们的分组的发送，以便产生重新组装的较大分组。在一个实施方式中，多个重组组件中的每一个维护指示本地存储的分组的一个或多个数据结构，以及存储在多个重组组件内的任何地方或其他地方的那些分组。当包括较大分组的所有较小分组都由分布式重排组件中的一个接收时，重新组装组件以协调的方式发送它们较小的分组，以产生原始较大的分组。

42. 发明授权

US07079545B1 System and method for simultaneous deficit round robin prioritization 有权
标题翻译：同时进行循环优先排序的系统和方法
公开(公告)号：US07079545B1
公开(公告)日：2006-07-18
申请号：US10022673
申请日：2001-12-17
申请人： Kenneth Yi Yun , Kevin Warren James
发明人： Kenneth Yi Yun , Kevin Warren James
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L47/50 , H04L47/527 , H04L47/6215 , H04L47/6225 , H04L47/6255 , H04L49/608 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： A system and method have been provided for prioritizing queued information packets having a variable number of cells. A simultaneous deficit round robin (DRR) analysis occurs in the course of several selection cycles. Each queue has an associated increment value. The packet lengths in each queue are simultaneously compared to an accumulation total in every selection cycle. If all the packets have lengths greater than their corresponding accumulation totals, each accumulation total is incremented and the selection process is repeated. If one of the information packets has a number of cells less than, or equal to its corresponding accumulation total, it is selected. In case multiple information packets are eligible, a variety of selection criteria can be used to break a tie. For example, the eligible information packet with the highest class of service (COS) can be selected. The information packet is completed transferred before another selection process is begun.
摘要翻译：已经提供了用于对具有可变数目的单元的排队信息分组进行优先排序的系统和方法。在几个选择周期的过程中，发生同时的赤字循环（DRR）分析。每个队列都有一个关联的增量值。每个队列中的分组长度同时与每个选择周期中的累积总和进行比较。如果所有数据包的长度大于其对应的累加总数，则每个累积总数将递增，并重复选择过程。如果其中一个信息包具有小于或等于其相应累积总数的小区数，则选择该信元。在多个信息包符合条件的情况下，可以使用各种选择标准来打破联系。例如，可以选择具有最高服务等级（COS）的合格信息包。在另一个选择过程开始之前，信息包被完成传送。

43. 发明授权

US07072298B2 Method and apparatus for rendering a cell-based switch useful for frame based protocols 有权
公开(公告)号：US07072298B2
公开(公告)日：2006-07-04
申请号：US10873550
申请日：2004-06-21
申请人： Harry V. Paul , Henry O. Gonzalez , Larry Cantwell
发明人： Harry V. Paul , Henry O. Gonzalez , Larry Cantwell
IPC分类号： G06F11/00 , H04J3/16
CPC分类号： H04L12/5601 , H04L47/6275 , H04L49/1576 , H04L49/25 , H04L49/3081 , H04L49/357 , H04L49/608 , H04L2012/5605 , H04L2012/5627 , H04L2012/5651 , H04L2012/5665 , H04L2012/5681 , H04Q11/0478 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/1332
摘要： A switch segments variable length frames into cells for transmission over a cell-based switch fabric and handles rate differences between the input data rate and the switch fabric data rate. The fabric handles multiple cell packets by maintaining a switch path until a certain number of cells are transmitted as indicated in a length field in the first data cell. The first cell contains a full data payload, and a length field value sufficient to handle a maximum length frame. Subsequent cells can contain less than a full data payload, with the number of valid bytes in the cell being indicated in the length field. The last cell used to segment the frame contains an end of frame indicator. The indicator signals the destination port side of the switch to terminate the packet path in the switch fabric prematurely—before the number of cells indicated in the first data cell.

44. 发明授权

US07020131B1 System and method for hierarchical switching 失效
标题翻译：分层交换的系统和方法
公开(公告)号：US07020131B1
公开(公告)日：2006-03-28
申请号：US10035835
申请日：2001-12-24
申请人： Kenneth Yi Yun , Kevin Warren James
发明人： Kenneth Yi Yun , Kevin Warren James
IPC分类号： H04L12/66 , H04L12/50 , H04L12/28 , H04Q11/00 , H04J3/02 , G06F13/00
CPC分类号： H04L49/153 , H04L12/5601 , H04L49/1576 , H04L49/608 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04Q2213/1302 , H04Q2213/1304
摘要： A system and method have been provided for hierarchically arbitrating in a broadband information switching network. The method promotes the fair and efficient distribution of information packets across the switch fabric that ultimately permits the switch to maximally match information packets to switch output addresses, at faster rates and higher throughput. The method comprises: accepting variably sized information packets at a plurality of switch inputs, that address a plurality of switch outputs; at each switch input, queuing the information packets into a plurality of queues; parsing the information packets into units of one cell; simultaneously arbitrating between each switch output and a plurality of available switch inputs, where an available input is defined to have at least one queue with an information packet addressing that particular switch output; selecting a queue; locking the link between switch inputs and switch outputs; and, transferring information packets across the links in units of one cell per master decision cycle.
摘要翻译：已经提供了一种用于在宽带信息交换网络中进行分级仲裁的系统和方法。该方法促进了跨交换结构的信息分组的公平和有效的分配，最终允许交换机以更快的速率和更高的吞吐量最大限度地匹配信息分组以切换输出地址。该方法包括：在多个交换机输入端接收可变大小的信息分组，其处理多个开关输出; 在每个交换机输入处，将信息分组排队成多个队列; 将信息包解析为一个单元的单元; 同时在每个开关输出和多个可用开关输入之间进行仲裁，其中可用输入被定义为具有至少一个具有寻址特定开关输出的信息分组的队列; 选择队列; 锁定开关输入和开关输出之间的连接; 并且以每个主决策周期的一个单元为单位在链路之间传送信息分组。

45. 发明授权

US07016366B2 Packet switch that converts variable length packets to fixed length packets and uses fewer QOS categories in the input queues that in the outout queues 失效
标题翻译：分组交换机，将可变长度数据包转换为固定长度数据包，并在输出队列中使用较少的QOS类别
公开(公告)号：US07016366B2
公开(公告)日：2006-03-21
申请号：US09813226
申请日：2001-03-20
申请人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Tsuguo Kato
发明人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Tsuguo Kato
IPC分类号： H04L12/28
CPC分类号： H04L49/30 , H04L47/10 , H04L47/15 , H04L47/20 , H04L47/2433 , H04L47/2441 , H04L47/29 , H04L47/30 , H04L47/32 , H04L47/50 , H04L47/60 , H04L47/627 , H04L49/101 , H04L49/201 , H04L49/205 , H04L49/254 , H04L49/3009 , H04L49/3045 , H04L49/3063 , H04L49/3072 , H04L49/3081 , H04L49/503 , H04L49/608 , H04L2012/5647 , H04L2012/5651 , H04L2012/5652 , H04L2012/5679 , H04L2012/5682
摘要： To achieve QoS control, drop control and multicast control of a variable-length packet at high speed in small scale hardware, a packet divider divides a variable-length packet into fixed-length packets, and an input buffer section stores the divided fixed-length packets into queues by output lines and by QoS classes. A large number of QoS classes are mapped into only two kinds of classes including a guaranteed bandwidth class for which an assigned bandwidth is guaranteed and a best effort class for which a surplus bandwidth is allocated, thereby to achieve scheduling at the input side by an inter-line scheduler. An output buffer section assembles a variable-length packet from fixed-length packets that have been obtained by switching at a switch section in an output buffer section. A QoS control is performed based on a packet length.
摘要翻译：为了在小规模硬件中高速实现可变长度分组的QoS控制，丢弃控制和组播控制，分组分配器将可变长度分组分成固定长度分组，并且输入缓冲部分存储分割的固定长度数据包通过输出行和QoS类进入队列。大量的QoS等级被映射到只有两种类型，包括保证分配的带宽的保证带宽等级，以及为其分配剩余带宽的最佳努力类，从而通过一个inter 线程调度器输出缓冲器部分通过在输出缓冲器部分中的切换部分处切换而获得的固定长度分组组装可变长度分组。基于分组长度执行QoS控制。

46. 发明申请

US20050047334A1 Fibre channel switch 失效
标题翻译：光纤通道开关
公开(公告)号：US20050047334A1
公开(公告)日：2005-03-03
申请号：US10873532
申请日：2004-06-21
申请人： Harry Paul , Anthony Tornetta , Henry Gonzalez , Larry Cantwell , Gregory Koellner , Steven Schmidt , Jereld Pearson , Jason Workman , James Wright , Scott Carlsen , Govindaswamy Nallur
发明人： Harry Paul , Anthony Tornetta , Henry Gonzalez , Larry Cantwell , Gregory Koellner , Steven Schmidt , Jereld Pearson , Jason Workman , James Wright , Scott Carlsen , Govindaswamy Nallur
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/26
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L49/101 , H04L49/251 , H04L49/3072 , H04L49/357 , H04L49/505 , H04L49/608 , H04L2012/5605 , H04L2012/5665 , H04L2012/5679 , H04L2012/5681 , H04L2012/5683
摘要： A Fibre Channel switch is presented that tracks the congestion status of destination ports in an XOFF mask at each input. A mapping is maintained between virtual channels on an ISL and the destination ports to allow changes in the XOFF mask to trigger a primitive to an upstream port that provides virtual channel flow control. The XOFF mask is also used to avoid sending frames to a congested port. Instead, these frames are stored on a single deferred queue and later processed in a manner designed to maintain frame ordering. A routing system is provided that applies multiple routing rules in parallel to perform line speed routing. The preferred switch fabric is cell based, with techniques used to manage path maintenance for variable length frames and to adapt to varying transmission rates in the system. Finally, the switch allows data and microprocessor communication to share the same crossbar network.
摘要翻译：提供了一个光纤通道交换机，可以在每个输入端跟踪XOFF掩码中目标端口的拥塞状态。在ISL的虚拟通道和目标端口之间维护映射，以允许XOFF掩码中的更改触发提供虚拟通道流控制的上游端口的基元。 XOFF掩码也用于避免向拥塞的端口发送帧。相反，这些帧被存储在单个延迟队列中，并且稍后以设计为维持帧排序的方式进行处理。提供了并行应用多个路由规则以执行线速度路由的路由系统。优选的交换结构是基于小区的，具有用于管理可变长度帧的路径维护并适应系统中变化的传输速率的技术。最后，交换机允许数据和微处理器通信共享相同的交叉网络。

47. 发明授权

US06836479B1 Variable length packet communication device 失效
标题翻译：可变长度分组通信设备
公开(公告)号：US06836479B1
公开(公告)日：2004-12-28
申请号：US09362134
申请日：1999-07-28
申请人： Kenichi Sakamoto , Nobuhito Matsuyama , Takeshi Aimoto , Noboru Endo , Koji Wakayama , Norihiko Moriwaki
发明人： Kenichi Sakamoto , Nobuhito Matsuyama , Takeshi Aimoto , Noboru Endo , Koji Wakayama , Norihiko Moriwaki
IPC分类号： H04L1228
CPC分类号： H04L49/30 , H04L12/5601 , H04L45/302 , H04L45/60 , H04L49/101 , H04L49/20 , H04L49/254 , H04L49/3009 , H04L49/3018 , H04L49/3027 , H04L49/508 , H04L49/608 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681
摘要： An input interface segments a variable length packet into plurality of fixed length cells and generates an internal switching information based on the header information of the variable length packet. The input interface transmits the information to a switch and, after that, transmits the cells as the following cells of the information to the switch. The switch performs switching processing to the succeeding cells based on the information. Therefore, the information is not added to the cells. When an input interface starts to transmit cells generated from a packet to its destination output interface through the switch, the switch is reserved until all the cells arrive at the output interfaces.
摘要翻译：输入接口将可变长度分组划分成多个固定长度单元，并且基于可变长度分组的报头信息生成内部切换信息。输入接口将信息发送给交换机，然后将信元作为信息的下列单元发送给交换机。交换机根据该信息对后续的小区进行切换处理。因此，信息不会添加到单元格中。当输入接口开始通过交换机将从数据包生成的单元传输到其目标输出接口时，保留交换机直到所有单元到达输出接口。

48. 发明授权

US06791947B2 In-line packet processing 有权
标题翻译：在线包处理
公开(公告)号：US06791947B2
公开(公告)日：2004-09-14
申请号：US09129137
申请日：1998-08-04
申请人： Rasoul Mirzazadeh Oskouy , Dennis C. Ferguson , Hann-Hwan Ju , Raymond Marcelino Manese Lim , Pradeep S. Sindhu , Sreeram Veeragandham , Jeff Zimmer , Michael Hui
发明人： Rasoul Mirzazadeh Oskouy , Dennis C. Ferguson , Hann-Hwan Ju , Raymond Marcelino Manese Lim , Pradeep S. Sindhu , Sreeram Veeragandham , Jeff Zimmer , Michael Hui
IPC分类号： H04L1256
CPC分类号： H04L45/74 , G06F11/08 , H04L1/0041 , H04L12/56 , H04L12/5601 , H04L29/06 , H04L45/00 , H04L45/20 , H04L45/60 , H04L47/6225 , H04L49/103 , H04L49/108 , H04L49/203 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/3063 , H04L49/3081 , H04L49/555 , H04L49/602 , H04L49/608 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324 , H04L2012/5652 , H04L2012/5679 , H04Q11/0478
摘要： A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.
摘要翻译：一种用于在通过包括路由器的网络在源和目的地之间传输数据分组的系统中的路由器路由数据包的同时处理数据分组的方法和装置。该方法包括在接收到数据分组并且将数据分组的任何部分传送到分组存储器之前接收数据分组和数据分组的预处理层报头数据。数据分组此后被存储在分组存储器中。确定通过路由器的路由，其包括描述网络中的下一个连接的下一跳索引。从分组存储器检索数据分组，并且在从存储器检索数据分组的同时，从下一跳索引构建数据分组的新层标题。在从路由器传送之前，将新层标头耦合到数据包。

49. 发明授权

US06763029B2 Low latency shared memory switch architecture 失效
标题翻译：低延迟共享存储器交换架构
公开(公告)号：US06763029B2
公开(公告)日：2004-07-13
申请号：US10286154
申请日：2002-10-31
申请人： Stephen Trevitt , Robert Hale Grant , David Book
发明人： Stephen Trevitt , Robert Hale Grant , David Book
IPC分类号： H04Q1104
CPC分类号： H04L49/608 , H04L49/103 , H04L49/108 , H04L49/351 , H04L49/357 , H04Q11/0421
摘要： A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.
摘要翻译：提出了一种用于操作时间分割共享存储器开关的方法和装置。该装置包括一个总线，用于在交换机的相应多个输入通道中接收多个数据帧。切片交叉点以时间分片的方式将多个数据帧应用于共享存储器。为共享存储器的每个部分建立时间片以交错，使得在任何时钟周期，正在访问一个存储器部分用于写入至少一些数据帧，并且在下一个时钟周期中，存储器部分被访问用于读取至少一部分数据。

50. 发明授权

US06611527B1 Packet switching apparatus with a common buffer 失效
标题翻译：具有公共缓冲区的分组交换设备
公开(公告)号：US06611527B1
公开(公告)日：2003-08-26
申请号：US09497210
申请日：2000-02-03
申请人： Norihiko Moriwaki , Mitsuhiro Wada , Takahiko Kozaki , Hiroaki Kasahara
发明人： Norihiko Moriwaki , Mitsuhiro Wada , Takahiko Kozaki , Hiroaki Kasahara
IPC分类号： H04L1228
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/608 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5684
摘要： A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register 20 and a read address register 30. The switch is also provided with a distributive pointer 22 for distributing cells in a flow to a plurality of address chains and a write address register selector 21, as well as a read pointer 32 for reading packets from a plurality of the address chains and a read address register selector 31 so as to read the packets through a pipeline with use of those plural address chains.
摘要翻译：在具有共享缓冲器的交换机中执行的地址管理中，将多个地址链分配给每个这样的流作为输出线，优先级控制等。每个地址链具有写入地址寄存器20和读取地址寄存器30.开关还具有分配指示器22，用于将流中的单元分配到多个地址链和写入地址寄存器选择器21 作为用于从多个地址链读取分组的读指针32和读地址寄存器选择器31，以便通过使用这些多个地址链的流水线读取分组。

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