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1. 发明授权

US07058751B2 Packet switch 失效
公开(公告)号：US07058751B2
公开(公告)日：2006-06-06
申请号：US09942980
申请日：2001-08-30
申请人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Masakatsu Nagata , Tsuguo Kato , Tetsuaki Wakabayashi
发明人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Masakatsu Nagata , Tsuguo Kato , Tetsuaki Wakabayashi
IPC分类号： G06F13/00
CPC分类号： H04L49/201 , H04L49/101 , H04L49/506
摘要： The packet switch performs a scheduling process by selecting a unicast packet or a multicast packet to be output from each of N input buffers such that input lines and output lines cannot conflict each other for a unicast packet, and such that the input lines cannot conflict each other for the multicast packet.

2. 发明授权

US06411620B1 Connectionless communication system 失效
标题翻译：无连接通信系统
公开(公告)号：US06411620B1
公开(公告)日：2002-06-25
申请号：US08970825
申请日：1997-11-14
申请人： Tadahiro Takase , Kazuo Hajikano , Takeshi Kawasaki , Toshio Shimoe , Tetsuo Tachibana , Teruaki Hagihara , Satoshi Kakuma , Masami Murayama , Ryuichi Takechi , Satoshi Kuroyanagi , Jyoei Kamoi , Hiroshi Tomonaga
发明人： Tadahiro Takase , Kazuo Hajikano , Takeshi Kawasaki , Toshio Shimoe , Tetsuo Tachibana , Teruaki Hagihara , Satoshi Kakuma , Masami Murayama , Ryuichi Takechi , Satoshi Kuroyanagi , Jyoei Kamoi , Hiroshi Tomonaga
IPC分类号： H04L1228
CPC分类号： H04L12/5602 , H04L2012/5616 , H04L2012/562 , H04L2012/5627 , H04L2012/563 , H04L2012/5645 , H04L2012/5652 , H04Q11/0478
摘要： The object of the present invention is accomodating local connectionless information (data that is immediately transferred without establishing a path to a receive side), such as LAN data in a local area network, by an asynchronous transfer mode (ATM) network using a connection-oriented communication system (which makes data transfers after verifying that a path to the receive side has been established), thereby performing efficient, fast routing of connectionless information. A connectionless communication system of the present invention is equipped with connectionless information cell assembly/deassembly means for bi-directional conversion between variable-length connectionless information and fixed-length connectionless cells, routing control means for analyzing a destination address of information in connectionless cells and controlling the routing of the connectionless cells; and an ATM network for connecting the connectionless information cell assembly/deassembly means and the routing control means by a permanent virtual channel serving as a fixed path and connecting the routing control means together by a virtual channel serving as a semi-fixed path, whereby connectionless information is segmented into connectionless cells and the connectionless information is exchanged within the ATM network in connectionless cell units.
摘要翻译：本发明的目的是通过异步传输模式（ATM）网络使用本地无连接信息（即，在不建立到接收侧的路径的情况下立即传送的数据），诸如局域网中的LAN数据，（在验证到接收侧的路径已经建立之后进行数据传输），从而执行无连接信息的有效，快速的路由。本发明的无连接通信系统配备有用于在可变长度无连接信息和固定长度无连接小区之间进行双向转换的无连接信息单元组合/拆卸装置，用于分析无连接小区中的信息的目的地地址的路由控制装置，以及控制无连接单元的路由; 以及用于通过用作固定路径的永久虚拟通道连接无连接信息单元组装/拆卸装置和路由控制装置并通过用作半固定路径的虚拟通道将路由控制装置连接在一起的ATM网络，由此无连接信息被分割成无连接小区，并且在无连接小区单元内的ATM网络内交换无连接信息。

3. 发明授权

US5878025A ATM switch and method for switching path by ATM switch 失效
标题翻译： ATM交换机和ATM交换机切换路径的方法
公开(公告)号：US5878025A
公开(公告)日：1999-03-02
申请号：US795297
申请日：1997-02-04
申请人： Hiroshi Tomonaga , Naoki Matsuoka , Masaaki Kawai , Masafumi Katoh , Yoshimi Watanabe , Hidenao Nakajima
发明人： Hiroshi Tomonaga , Naoki Matsuoka , Masaaki Kawai , Masafumi Katoh , Yoshimi Watanabe , Hidenao Nakajima
IPC分类号： H04Q3/52 , H04L1/22 , H04L12/28 , H04L12/70 , H04L12/801 , H04L12/911 , H04L12/931 , H04Q11/00 , H04L12/56
CPC分类号： H04L1/22 , H04L12/5601 , H04L49/108 , H04L49/1553 , H04L49/1584 , H04L49/255 , H04L49/256 , H04L49/405 , H04Q11/0001 , H04L2012/5605 , H04L2012/5672
摘要： A plurality of switching modules arrayed in a plurality of columns and in at least one row switch over paths in accordance with path data contained in cells to transfer inputted data to a target line on the cell-unit. One or more path switching units are provided between two adjacent columns of switching modules among plural columns of switching modules and switch paths between the respective switching modules, disposed in a side-by-side relationship in a row direction, of one column of switching modules of the two adjacent columns of switching modules and the respective switching modules, disposed in the side-by-side relationship in the row direction, of the other column of the two adjacent columns of switching modules.
摘要翻译：多个切换模块，其按照包含在单元中的路径数据在多个列中和至少一个行中切换至多个行，以将输入的数据传送到单元单元上的目标行。一列或多路路径切换单元设置在多列开关模块中的两列相邻的开关模块列之间，并且在一列交换模块之间并列设置的各个开关模块之间的开关路径在交替模块的两个相邻列的另一个列中的交替模块的两个相邻列和相应的交换模块以行方向并排的关系设置。

4. 发明授权

US08432925B2 Apparatus and method for controlling buffering of an arrival packet 有权
标题翻译：用于控制到达分组的缓冲的装置和方法
公开(公告)号：US08432925B2
公开(公告)日：2013-04-30
申请号：US12404502
申请日：2009-03-16
申请人： Kazuto Nishimura , Hiroshi Tomonaga , Akihiro Hata , Masamichi Kasa
发明人： Kazuto Nishimura , Hiroshi Tomonaga , Akihiro Hata , Masamichi Kasa
IPC分类号： H04L12/56
CPC分类号： H04L47/283 , H04L47/10 , H04L47/32 , H04L49/505
摘要： An apparatus for controlling buffering of an arrival packet. The apparatus includes a packet buffer for temporarily storing each of one or more packets to be transmitted in association with an arrival time thereof, and a packet discard section for determining an arrival packet to be discarded or to be stored in the packet buffer, based on a discard condition defined by using a packet residence time that is calculated on the basis of one or more residence times of one or more packets staying in the packet buffer, wherein the arrival packet is defined as a packet that has newly arrived at the apparatus.
摘要翻译：一种用于控制到达分组的缓冲的装置。该装置包括：分组缓冲器，用于临时存储与其到达时间相关联的要发送的一个或多个分组中的每一个;以及分组丢弃部分，用于基于丢弃或要存储在分组缓冲器中的到达分组，基于通过使用基于停留在分组缓冲器中的一个或多个分组的一个或多个停留时间计算的分组停留时间定义的丢弃条件，其中到达分组被定义为新到达该设备的分组。

5. 发明授权

US08306045B2 Packet forwarding apparatus and method for discarding packets 有权
标题翻译：用于丢弃分组的分组转发装置和方法
公开(公告)号：US08306045B2
公开(公告)日：2012-11-06
申请号：US12361655
申请日：2009-01-29
申请人： Akihiro Hata , Hiroshi Tomonaga , Katsumi Imamura
发明人： Akihiro Hata , Hiroshi Tomonaga , Katsumi Imamura
IPC分类号： G06F3/00 , G06F5/00 , H04L12/28 , H04L12/56
CPC分类号： H04L47/10 , H04L47/283 , H04L47/32 , H04L49/254 , H04L49/503 , H04L49/90 , H04L49/9047 , H04L49/9078
摘要： The packet forwarding apparatus of the present invention includes a packet buffer for temporarily storing packets to be forwarded, a timer for measuring the time of every predetermined unit period, a plurality of first queues corresponding to each of a plurality of address groups that form the packet buffer, a plurality of second queues that are provided corresponding to the property of the packets, a first controller for executing the writing of the packets, and a second controller for executing the discarding of the packets. According to this invention, through managing the first queues and the second queues, packets in the packet buffer can be discarded without the packets being read from the packet buffer.
摘要翻译：本发明的分组转发装置包括用于临时存储要转发的分组的分组缓冲器，用于测量每个预定单位周期的时间的定时器，对应于形成分组的多个地址组中的每一个的多个第一队列缓冲器，对应于分组的属性提供的多个第二队列，用于执行分组的写入的第一控制器，以及用于执行丢弃分组的第二控制器。根据本发明，通过管理第一队列和第二队列，可以丢弃分组缓冲器中的分组，而不从分组缓冲器读取分组。

6. 发明授权

US07366165B2 Input line interface device and packet communication device 有权
标题翻译：输入线路接口设备和分组通信设备
公开(公告)号：US07366165B2
公开(公告)日：2008-04-29
申请号：US10079082
申请日：2002-02-19
申请人： Kenichi Kawarai , Masakatsu Nagata , Hiroshi Tomonaga , Naoki Matsuoka , Tsuguo Kato
发明人： Kenichi Kawarai , Masakatsu Nagata , Hiroshi Tomonaga , Naoki Matsuoka , Tsuguo Kato
IPC分类号： H04Q11/00
CPC分类号： H04L49/9094 , H04L12/46 , H04L45/60 , H04L47/2441 , H04L49/30 , H04L49/90
摘要： An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.
摘要翻译：一种输入线接口装置，用于有效地适应来自高速线路的分组，并减少由路由控制引起的后台处理负担。分组分配部分分割可变长度分组，将分组分配给并行，并输出分组。流组分类部分将每个并行线路上的分组分组为流组。序列号给出部分给出与流组相对应或独立于流组的分组序列号。缓冲部分将缓冲器中已经给出序列号的分组存储在缓冲器中，或者从缓冲器中读出它们以对流组中的分组进行序列控制。流分离交换机根据流组分离报文，并输出报文。

7. 发明授权

US06920145B2 Packet switch device and scheduling control method 失效
标题翻译：分组交换机和调度控制方法
公开(公告)号：US06920145B2
公开(公告)日：2005-07-19
申请号：US09759181
申请日：2001-01-12
申请人： Naoki Matsuoka , Hiroshi Tomonaga , Kenichi Kawarai
发明人： Naoki Matsuoka , Hiroshi Tomonaga , Kenichi Kawarai
IPC分类号： H04L12/931 , H04L12/937 , H04L12/56
CPC分类号： H04L49/608 , H04L49/205 , H04L49/254 , H04L49/30 , H04L49/3063 , H04L49/503 , H04L49/508 , H04L2012/5679
摘要： A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers. Further, in the scheduled sending process executed in a number of processes, in parallel, the device does not select the input line sending the fixed length packets corresponding to the same frame, and, after determining a selection, the device maintains the selection of the same input line until the completion of sending the fixed length packets corresponding to the same frame.
摘要翻译：一种具有多个输入缓冲器的分组交换设备; 分组交换机多个调度器，其具有流水线调度处理模块，其中与输出线数相对应的多个时间单元在来自输入缓冲器的固定长度分组的调度发送过程中被消耗，并且其中调度发送过程以并行处理对应于输入线数量的处理次数，具有发送状态管理模块，其中为每个输入行管理构成一帧的固定长度分组的发送状态，并且提供相应的到任何输出线; 以及至少一个结果通知模块，用于从所述多个调度器中的每个调度器执行的所调度的发送处理通知结果信息的输入缓冲器。此外，在多个处理中执行的调度发送处理中，并行地，设备不选择发送对应于同一帧的固定长度分组的输入行，并且在确定选择之后，设备保持对相同的输入行直到完成发送对应于同一帧的固定长度数据包。

8. 发明授权

US06687225B1 Bandwidth control apparatus 失效
标题翻译：带宽控制装置
公开(公告)号：US06687225B1
公开(公告)日：2004-02-03
申请号：US09421465
申请日：1999-10-19
申请人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Naotoshi Watanabe , Yasuhiro Ooba , Hichiro Hayami
发明人： Kenichi Kawarai , Hiroshi Tomonaga , Naoki Matsuoka , Naotoshi Watanabe , Yasuhiro Ooba , Hichiro Hayami
IPC分类号： H04L1256
CPC分类号： H04Q11/0478 , H04L12/5601 , H04L12/5602 , H04L2012/5625 , H04L2012/5632 , H04L2012/5651 , H04L2012/568
摘要： The invention relates to a bandwidth control apparatus in ATM equipment, for inserting management cells such as OAM cells, the control apparatus being configured to secure a bandwidth for the insertion of a management cell such as an OAM cell when the need arises, while guaranteeing the service quality of user cells, thereby making effective use of network resources for a best effort service such as ABR or UBR. The bandwidth control apparatus comprises a cell insertion block 1-10 for inserting a management cell such as an OAM cell and a shaping block 1-20 for performing user cell shaping, wherein the cell insertion block 1-10 issues an empty cell request when a cell insertion request occurs, the shaping block 1-20, upon receiving the empty cell insertion request, inserts an empty cell in a user cell stream being output from a shaping buffer 1-22, and the cell insertion block 1-10 writes a management cell such as an OAM cell over the empty cell inserted on a cell highway 1-30, thus sending the management cell out on the cell highway 1-30.
摘要翻译：本发明涉及一种ATM设备中的带宽控制装置，用于插入诸如OAM小区的管理小区，该控制装置被配置为在需要时保证用于插入诸如OAM小区之类的管理小区的带宽，同时保证用户单元的服务质量，从而有效利用网络资源实现最佳服务，如ABR或UBR。带宽控制装置包括用于插入诸如OAM小区的管理小区的小区插入块1-10和用于进行用户小区整形的整形块1-20，其中，当小区插入块1-10发出空单元请求时，单元插入请求发生时，整形块1-20在接收到空单元插入请求时，将其从一个整形缓冲器1-22输出的用户单元流中插入一个空单元，并且单元插入块1-10写入管理小区，例如插入单元高速公路1-30上的空单元上的OAM单元，从而将单元高速公路1-30上的管理单元发送出去。

9. 发明授权

US5610913A Switching equipment for performing a switching operation for a high-speed packet in broadband Integrated Services Digital Network 失效
标题翻译：用于在宽带综合业务数字网络中执行高速分组的切换操作的交换设备
公开(公告)号：US5610913A
公开(公告)日：1997-03-11
申请号：US401032
申请日：1995-03-08
申请人： Hiroshi Tomonaga , Naoki Matsuoka , Miwako Watanabe , Satoshi Kuroyanagi , Yutaka Ezaki , Akira Hakata , Ryuichi Takechi , Masaaki Kawai
发明人： Hiroshi Tomonaga , Naoki Matsuoka , Miwako Watanabe , Satoshi Kuroyanagi , Yutaka Ezaki , Akira Hakata , Ryuichi Takechi , Masaaki Kawai
IPC分类号： H04J3/00 , H04L12/02 , H04L12/70 , H04L12/823 , H04L12/931 , H04L12/935 , H04L12/951 , H04Q3/00 , H04Q11/00 , H04L12/56
CPC分类号： H04L49/25 , H04L49/255 , H04L49/3009 , H04L49/3081 , H04L49/552 , H04L2012/5625 , H04L2012/5627 , H04L2012/5636 , H04L2012/5639 , H04L49/15 , H04L49/30 , H04L49/503 , H04Q2011/0015 , H04Q2011/0081
摘要： Switching equipment in provided for performing a switching process of a fixed length cell consisting of data and a cell header. A line interface provided in the switching equipment accommodates a plurality of lines and, at the same time, processes the data from each line on a cell unit. The line interface includes individual units and a common unit. The individual units are individually connected to the plurality of lines accommodated therein and individually process the cells. The common unit is connected to the individual units and, at the same time, effects batch-processing of the cells processed by the individual units.
摘要翻译：交换设备用于执行由数据和单元头组成的固定长度单元的切换处理。设置在交换设备中的线路接口容纳多条线路，并且同时处理来自小区单元的每条线路的数据。线路接口包括单个单元和公共单元。各个单元分别连接到容纳在其中的多条线，并分别处理单元。公共单元连接到各个单元，并且同时影响由各个单元处理的单元的批处理。

10. 发明授权

US08937962B2 Packet buffering device and packet discarding method 有权
标题翻译：数据包缓存装置和数据包丢弃方法
公开(公告)号：US08937962B2
公开(公告)日：2015-01-20
申请号：US13195109
申请日：2011-08-01
申请人： Hiroshi Tomonaga , Kazuto Nishimura
发明人： Hiroshi Tomonaga , Kazuto Nishimura
IPC分类号： H04L12/801 , H04L12/853 , H04L12/841 , H04L12/835 , H04L12/823 , H04L29/06
CPC分类号： H04L47/10 , H04L47/2416 , H04L47/28 , H04L47/30 , H04L47/32 , H04L65/80
摘要： A packet buffering device includes: a queue for temporarily holding an arriving packet; a residence time predicting unit which predicts a length of time during which the arriving packet will reside in the queue; and a packet discarding unit which discards the arriving packet when the length of time predicted by the residence time predicting unit exceeds a first reference value.
摘要翻译：分组缓存装置包括：用于临时保持到达分组的队列; 停留时间预测单元，其预测到达的分组将驻留在队列中的时间长度; 以及分组丢弃单元，当由所述停留时间预测单元预测的时间长度超过第一参考值时，丢弃所述到达分组。

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