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41. 发明申请

US20020163072A1 Method for bonding wafers to produce stacked integrated circuits 审中-公开
标题翻译：用于接合晶片以产生堆叠集成电路的方法
公开(公告)号：US20020163072A1
公开(公告)日：2002-11-07
申请号：US09847667
申请日：2001-05-01
发明人： Subhash Gupta , Paul Kwok Keung Ho , Sangki Hong
IPC分类号： H01L021/461 , H01L023/12 , H01L023/544
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/50 , H01L2224/08148 , H01L2224/80203 , H01L2224/8083 , H01L2224/80895 , H01L2225/06513 , H01L2225/06541 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit. In this case, the electrical conducting vias are also connected to various circuit elements by metallic conductors disposed in a dielectric layer that covers the circuit layer. A plurality of bonding pads are provided on one surface of the integrated circuit wafer. These pads may be part of the vias. These pads preferably extend above the surface of the integrated circuit wafer. A stacked integrated circuit according to the present invention is constructed by bonding two integrated circuit wafers together utilizing the bonding pads. One of the integrated circuit wafers is then thinned to a predetermined thickness determined by the depth of the vias by chemical/mechanical polishing (CMP) of the surface of that integrated circuit wafer that is not bonded to the other integrated circuit wafer, the stop layer in the vias preventing the CMP from removing wafer material that is within the first distance from the first surface of the substrate of the wafer being thinned.
摘要翻译：一种集成电路晶片元件和用于将其结合以产生堆叠集成电路的改进方法。根据本发明的集成电路晶片包括具有由晶片材料构成的第一和第二表面的基板，所述第一表面具有包括在其上构成的集成电路元件的电路层。多个通孔从第一表面延伸穿过电路层，并在离开第一表面的第一距离处终止在基板中。通孔包括位于每个通孔底部的停止层，该停止层由比晶片材料更耐化学/机械抛光（CMP）的止动材料构成。通孔可以填充有导电材料，以在堆叠集成电路中的各个电路层之间提供垂直连接。在这种情况下，导电通孔也通过布置在覆盖电路层的电介质层中的金属导体连接到各种电路元件。多个接合焊盘设置在集成电路晶片的一个表面上。这些焊盘可以是通孔的一部分。这些焊盘优选地在集成电路晶片的表面上方延伸。根据本发明的堆叠集成电路是通过使用接合焊盘将两个集成电路晶片结合在一起而构成的。然后通过化学/机械抛光（CMP）将集成电路晶片之一变薄到由通孔的深度确定的预定厚度，该集成电路晶片的表面未结合到另一集成电路晶片，停止层在通孔中，防止CMP从晶片的衬底的第一表面的第一距离内移除晶片材料。

42. 发明授权

US06458681B1 Method for providing void free layer for semiconductor assemblies 有权
标题翻译：为半导体组件提供无空隙层的方法
公开(公告)号：US06458681B1
公开(公告)日：2002-10-01
申请号：US09638079
申请日：2000-08-14
申请人： Thomas H. DiStefano , Joseph Fjelstad
发明人： Thomas H. DiStefano , Joseph Fjelstad
IPC分类号： H01L2144
CPC分类号： H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/49572 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/08225 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/80203 , H01L2224/80207 , H01L2224/81192 , H01L2224/81904 , H01L2224/83209 , H01L2224/9212 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/80001 , H01L2224/81
摘要： A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.
摘要翻译：一种利用可固化密封剂为一个或多个倒装芯片组件或一个或多个微电子部件提供基本无空隙的方法。还公开了将密封剂注入到组件中的方法以及处理微电子部件以形成无空隙层的方法。

43. 发明授权

US6107123A Methods for providing void-free layers for semiconductor assemblies 有权
标题翻译：为半导体组件提供无空隙层的方法
公开(公告)号：US6107123A
公开(公告)日：2000-08-22
申请号：US188599
申请日：1998-11-09
申请人： Thomas H. Distefano , Joseph Fjelstad
发明人： Thomas H. Distefano , Joseph Fjelstad
IPC分类号： H01L21/56 , H01L21/68 , H01L23/31 , H01L23/495 , H01L21/44
CPC分类号： H01L21/568 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/3107 , H01L23/3114 , H01L23/49572 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/08225 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/80203 , H01L2224/80207 , H01L2224/81192 , H01L2224/81904 , H01L2224/83209 , H01L2224/9212 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15311
摘要： A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component enapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer is created.
摘要翻译：在未固化或部分固化的微电子元件助剂和粘合剂/芯片附着层中去除空隙和气泡的方法。通过施加均匀的压力（等静压或静水压）和能量使得产生基本上无空隙/无气泡的中间层，基本上消除了微电子部件和支撑基板之间的间隙内的密封空隙或气泡。

44. 发明申请

US20180277493A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180277493A1
公开(公告)日：2018-09-27
申请号：US15694970
申请日：2017-09-04
申请人： Toshiba Memory Corporation
发明人： Masaya SHIMA , Eiji TAKANO , Ippei KUME , Yuki NODA
IPC分类号： H01L23/00 , H01L25/00 , H01L21/768 , H01L21/78 , H01L25/065 , H01L23/48 , H01L23/31
CPC分类号： H01L23/562 , H01L21/67092 , H01L21/76898 , H01L21/78 , H01L21/8221 , H01L23/3171 , H01L23/4012 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/24 , H01L24/80 , H01L24/82 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/08146 , H01L2224/1146 , H01L2224/1147 , H01L2224/13023 , H01L2224/13025 , H01L2224/13111 , H01L2224/13147 , H01L2224/24105 , H01L2224/24147 , H01L2224/244 , H01L2224/73251 , H01L2224/73259 , H01L2224/80203 , H01L2224/80801 , H01L2224/82031 , H01L2224/821 , H01L2224/9202 , H01L2224/9222 , H01L2224/94 , H01L2225/06544 , H01L2225/06586 , H01L2924/00014 , H01L2924/00012 , H01L2224/80001 , H01L2224/11 , H01L2224/82 , H01L2224/08 , H01L2224/24
摘要： A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.

46. 发明授权

US09761561B2 Edge structure for backgrinding asymmetrical bonded wafer 有权
公开(公告)号：US09761561B2
公开(公告)日：2017-09-12
申请号：US14660949
申请日：2015-03-18
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Ranjan Rajoo , Kai Chong Chan
IPC分类号： H01L21/304 , H01L25/065 , H01L25/00 , H01L21/768
CPC分类号： H01L25/0657 , H01L21/304 , H01L21/76898 , H01L24/08 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2224/08145 , H01L2224/32145 , H01L2224/33181 , H01L2224/73251 , H01L2224/80203 , H01L2224/8312 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2224/83862 , H01L2224/83874 , H01L2224/8389 , H01L2224/92 , H01L2224/9202 , H01L2224/9222 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/10156 , H01L2924/1461 , H01L2924/00014 , H01L2224/80 , H01L2224/83 , H01L2224/08 , H01L2224/32 , H01L2224/0231 , H01L2224/03 , H01L2224/11
摘要： Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes edge and non-edge regions. The wafer includes a plurality of devices and partially processed TSV contacts disposed in the non-edge region and a groove disposed at the edge region. The groove enables edges of the wafer to be automatically trimmed off as the wafer is subject to a back-grinding planarization process to expose the TSV contacts in the non-edge region of the wafer.

47. 发明申请

US20170221856A1 METHOD FOR BONDING SUBSTRATES TOGETHER, AND SUBSTRATE BONDING DEVICE 审中-公开
公开(公告)号：US20170221856A1
公开(公告)日：2017-08-03
申请号：US15519542
申请日：2015-10-19
申请人： BONDTECH CO., LTD.
发明人： Akira YAMAUCHI
IPC分类号： H01L23/00 , H01L21/683 , H01L21/67
CPC分类号： H01L24/83 , B23K20/023 , B23K20/233 , B23K20/24 , B23K37/0408 , B23K37/047 , B23K2101/40 , B23K2103/50 , H01L21/187 , H01L21/67092 , H01L21/67259 , H01L21/68 , H01L21/6831 , H01L21/6838 , H01L21/68735 , H01L23/544 , H01L24/75 , H01L24/80 , H01L24/94 , H01L2223/54426 , H01L2224/08145 , H01L2224/08146 , H01L2224/7501 , H01L2224/75102 , H01L2224/75251 , H01L2224/75252 , H01L2224/75272 , H01L2224/75303 , H01L2224/75305 , H01L2224/757 , H01L2224/75701 , H01L2224/75702 , H01L2224/75704 , H01L2224/75705 , H01L2224/75724 , H01L2224/75725 , H01L2224/75744 , H01L2224/75745 , H01L2224/75753 , H01L2224/759 , H01L2224/75901 , H01L2224/7592 , H01L2224/75981 , H01L2224/80012 , H01L2224/80013 , H01L2224/8003 , H01L2224/80047 , H01L2224/8009 , H01L2224/8013 , H01L2224/80132 , H01L2224/80203 , H01L2224/80213 , H01L2224/80893 , H01L2224/80895 , H01L2224/80896 , H01L2224/80907 , H01L2224/80908 , H01L2224/80986 , H01L2224/83009 , H01L2224/8309 , H01L2224/83896 , H01L2224/83908 , H01L2224/94 , H01L2924/00012 , H01L2224/80 , H01L2924/00014 , H01L2224/8001 , H01L2224/80009 , H01L2224/80121
摘要： A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

48. 发明授权

US09704820B1 Semiconductor manufacturing method and associated semiconductor manufacturing system 有权
公开(公告)号：US09704820B1
公开(公告)日：2017-07-11
申请号：US15054907
申请日：2016-02-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Xin-Hua Huang , Yung-Lung Lin , Ping-Yin Liu , Chia-Shiung Tsai
IPC分类号： H01L21/67 , H01L23/00 , H01L21/50 , H01L21/02 , H01L21/687
CPC分类号： H01L21/68764 , H01L21/02049 , H01L21/187 , H01L21/2007 , H01L21/76251 , H01L22/12 , H01L22/20 , H01L24/05 , H01L24/08 , H01L24/799 , H01L24/80 , H01L24/94 , H01L24/98 , H01L2224/04 , H01L2224/05624 , H01L2224/05647 , H01L2224/08145 , H01L2224/80203 , H01L2224/80801 , H01L2224/80805 , H01L2224/80893 , H01L2224/80895 , H01L2224/80896 , H01L2224/80908 , H01L2224/80948 , H01L2224/80986 , H01L2224/94 , H01L2224/80 , H01L2924/00014 , H01L2224/08 , H01L2224/808
摘要： A semiconductor manufacturing method is disclosed. The method includes: providing a first wafer and a second wafer, wherein the first wafer and the second wafer are bonded together; submerging the bonded first and second wafers in an ultrasonic transmitting medium; producing ultrasonic waves; and directing the ultrasonic waves to the bonded first and second wafers through the ultrasonic transmitting medium for a predetermined time period. An associated semiconductor manufacturing system for at least weakening a bonding strength of bonded wafers is also disclosed.

49. 发明申请

US20170186733A1 Method for Aligning Micro-Electronic Components 有权
公开(公告)号：US20170186733A1
公开(公告)日：2017-06-29
申请号：US15457744
申请日：2017-03-13
申请人： IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
发明人： Vikas Dubey , Ingrid De Wolf , Eric Beyne
IPC分类号： H01L25/065 , H01L25/00 , H01L23/31 , H01L23/00 , H01L23/528
CPC分类号： H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
摘要： Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.

50. 发明授权

US09673147B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US09673147B2
公开(公告)日：2017-06-06
申请号：US15005377
申请日：2016-01-25
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kenro Nakamura , Hirokazu Ezawa
IPC分类号： H01L21/302 , H01L23/535 , H01L23/48 , H01L23/532 , H01L25/065 , H01L23/00 , H01L25/00 , H01L23/528 , H01L21/768
CPC分类号： H01L23/535 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/528 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/03616 , H01L2224/0401 , H01L2224/05006 , H01L2224/05026 , H01L2224/05547 , H01L2224/05557 , H01L2224/05562 , H01L2224/05571 , H01L2224/05572 , H01L2224/05639 , H01L2224/05647 , H01L2224/05686 , H01L2224/08147 , H01L2224/08148 , H01L2224/10126 , H01L2224/11462 , H01L2224/1147 , H01L2224/11616 , H01L2224/13009 , H01L2224/13017 , H01L2224/13022 , H01L2224/80203 , H01L2224/8083 , H01L2224/81193 , H01L2224/81203 , H01L2224/8183 , H01L2225/06513 , H01L2225/06541 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2924/04941
摘要： A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.

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