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41. 发明授权

US08760916B2 Circuit and system of using at least one junction diode as program selector for memories 有权
标题翻译：使用至少一个结二极管作为存储器的程序选择器的电路和系统
公开(公告)号：US08760916B2
公开(公告)日：2014-06-24
申请号：US13026835
申请日：2011-02-14
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C11/15
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for memory cells that can be programmed based on direction of current flow. These cells are MRAM, RRAM, CBRAM, or other memory cells that have a programmable resistive element coupled to a P terminal of a first diode and to an N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the first diodes and the P terminals of the second diodes in a row connected as wordline(s) and the resistive elements in a column connected as a bitline. By applying a high voltage to a selected bitline and a low voltage to a selected wordline to turn on the first diode while disabling the second diode, a selected cell can be programmed into one state. Similarly, by applying a low voltage to a selected bitline and a high voltage to a selected wordline to turn on the second diode while disabling the first diode, a selected cell can be programmed into another state. The data in the resistive memory cell can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).
摘要翻译：在标准CMOS逻辑工艺中制造的至少一个结二极管可用作可根据电流方向编程的存储器单元的程序选择器。这些单元是具有耦合到第一二极管的P端子和第二二极管的N端子的可编程电阻元件的MRAM，RRAM，CBRAM或其它存储器单元。二极管可以由N阱上的P +和N +有源区域构成，作为二极管的P和N端子。存储单元可用于构建二维存储器阵列，其中第一二极管的N端和第二二极管的P端作为字线连接，并且作为位线连接的列中的电阻元件作为位线。通过将高电压施加到所选择的位线和低电压到所选择的字线以在禁用第二二极管的同时接通第一二极管，所选择的单元可以被编程为一个状态。类似地，通过将低电压施加到所选择的位线和高电压到所选择的字线以在禁用第一二极管的同时接通第二二极管，所选择的单元可以被编程到另一状态。也可以通过打开所选择的字线来读取电阻存储器单元中的数据，以将选定的位线耦合到读出放大器。字线可以具有通过导电接触或通孔耦合到低电阻率全局字线的高电阻率局部字线。

42. 发明授权

US08760904B2 One-Time Programmable memories using junction diodes as program selectors 有权
标题翻译：一次性使用结二极管作为程序选择器的可编程存储器
公开(公告)号：US08760904B2
公开(公告)日：2014-06-24
申请号：US13026771
申请日：2011-02-14
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/00 , H01L23/52
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The OTP device has an OTP element coupled to the diode. The OTP device can be used to construct a two-dimensional OTP memory with the N terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline.
摘要翻译：以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝，二极管可以由N阱上的P +和N +有源区域构成，作为二极管的P和N端子。 OTP器件具有耦合到二极管的OTP元件。 OTP设备可以用于构建二维OTP存储器，其中连接作为字线的二极管的N个端子和作为位线连接的列中的OTP元件。

43. 发明申请

US20140071780A1 E-FUSE ARRAY CIRCUIT 有权
标题翻译：电子保险丝阵列电路
公开(公告)号：US20140071780A1
公开(公告)日：2014-03-13
申请号：US13610802
申请日：2012-09-11
申请人： Sungju SON , Youncheul Kim , Sungho Kim , Dongue Ko
发明人： Sungju SON , Youncheul Kim , Sungho Kim , Dongue Ko
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/00 , G11C17/16 , G11C17/165 , G11C29/027 , G11C29/787 , G11C2229/763 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.
摘要翻译：电子熔丝阵列电路包括：垂直栅极类型的电子熔丝晶体管，其被配置为具有用于接收编程栅极线的电压并且在漏极端子和源极端子之间浮置的栅极的栅极; 以及掩埋栅极型选择晶体管，其配置为具有用于接收字线栅极线的电压的栅极，并且利用位线将漏极端子和源极端子之间的另一个电连接/断开。

44. 发明授权

US08637957B1 Low cost anti-fuse structure 失效
标题翻译：低成本的反熔丝结构
公开(公告)号：US08637957B1
公开(公告)日：2014-01-28
申请号：US13552293
申请日：2012-07-18
申请人： Chih-Chao Yang , Stephen M. Gates
发明人： Chih-Chao Yang , Stephen M. Gates
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , G11C17/165 , H01L21/7684 , H01L21/76877 , H01L21/76882 , H01L21/76883 , H01L23/5226 , H01L23/5283 , H01L23/53214 , H01L23/53219 , H01L23/53228 , H01L23/53233 , H01L23/53247 , H01L23/5329 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.
摘要翻译：提供一种抗熔丝结构，其中抗熔丝材料衬垫嵌入设置在互连电介质材料内的一个开口内。反熔丝材料衬垫位于第一导电金属和第二导电金属之间，第一导电金属和第二导电金属也存在于开口内。扩散阻挡衬里将第一导电金属与互连电介质材料的任何部分分开。反熔丝结构横向邻近形成在与反熔丝结构相同的互连电介质材料内的互连结构。

45. 发明申请

US20130308366A1 Circuit and System of Using Junction Diode as Program Selector for One-Time Programmable Devices 有权
标题翻译：使用结二极管作为一次性可编程器件的程序选择器的电路和系统
公开(公告)号：US20130308366A1
公开(公告)日：2013-11-21
申请号：US13954831
申请日：2013-07-30
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/16
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact.
摘要翻译：以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， OTP器件具有耦合到存储器单元中的二极管的OTP元件。二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。通过将高电压施加到二极管的P端子并将二极管的N端子切换到低电压适当的持续时间，与程序选择器串联的OTP元件的电流可能改变电阻状态。通过使用虚拟MOS栅极，SBL或STI / LOCOS隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。如果电阻元件是基于CMOS栅极材料的互连熔丝，则电阻元件可通过邻接触点耦合到P +有源区，使得元件，有源区和金属以单个矩形接触连接。

46. 发明授权

US08559208B2 Programmably reversible resistive device cells using polysilicon diodes 有权
标题翻译：使用多晶硅二极管的可编程电阻器件单元
公开(公告)号：US08559208B2
公开(公告)日：2013-10-15
申请号：US13026704
申请日：2011-02-14
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C11/00
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices such as PCRAM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. By applying a voltage or a current between a reversible resistive element and the N-terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. On the polysilicon diode, the spacing and doping level of a gap between the P- and N-implants can be controlled for different breakdown voltages and leakage currents. The Silicide Block Layer (SBL) can be used to block silicide formation on the top of polysilicon to prevent shorting.
摘要翻译：以标准CMOS逻辑工艺制造的多晶硅二极管可用作可逆电阻器件（如PCRAM，RRAM，CBRAM或其他存储器单元）的程序选择器。可逆电阻器件具有耦合到二极管的可逆电阻元件。二极管可以由多晶硅上的P + / N +种植体构成，作为程序选择器。通过在可逆电阻元件和二极管的N端之间施加电压或电流，可逆电阻器件可以以可逆的方式基于幅度，持续时间，电压限制或电流限制被编程到不同的状态。在多晶硅二极管上，可以对不同的击穿电压和漏电流来控制P型和N型注入之间的间隙和掺杂水平。硅化物阻挡层（SBL）可用于阻挡多晶硅顶部的硅化物形成以防止短路。

47. 发明授权

US08514606B2 Circuit and system of using junction diode as program selector for one-time programmable devices 有权
标题翻译：使用结二极管作为一次性可编程器件的程序选择器的电路和系统
公开(公告)号：US08514606B2
公开(公告)日：2013-08-20
申请号：US13026752
申请日：2011-02-14
申请人： Shine C. Chung
发明人： Shine C. Chung
IPC分类号： G11C17/00
CPC分类号： H01L27/2436 , G11C8/14 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C17/16 , G11C17/165 , G11C2013/0073 , G11C2213/72 , G11C2213/74 , H01L27/224 , H01L27/2409 , H01L29/785 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146
摘要： Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact.
摘要翻译：以标准CMOS逻辑工艺制造的结二极管可用作一次性可编程（OTP）器件的程序选择器，例如电熔丝，接触/通孔保险丝，接触/通孔抗熔丝或栅极氧化物击穿反熔丝， OTP器件具有耦合到存储器单元中的二极管的OTP元件。二极管可以由N阱上的P +和N +有源区构成，作为二极管的P和N端。通过将高电压施加到二极管的P端子并将二极管的N端子切换到低电压适当的持续时间，与程序选择器串联的OTP元件的电流可能改变电阻状态。通过使用虚拟MOS栅极，SBL或STI / LOCOS隔离，二极管的P +有源区可以与N阱中的N +有源区隔离。如果电阻元件是基于CMOS栅极材料的互连熔丝，则电阻元件可通过邻接触点耦合到P +有源区，使得元件，有源区和金属以单个矩形接触连接。

48. 发明申请

US20130208525A1 SOFT BREAKDOWN MODE, LOW VOLTAGE, LOW POWER ANTIFUSE-BASED NON-VOLATILE MEMORY CELL 有权
标题翻译：软断开模式，低电压，低功耗抗体基于非易失性存储器单元
公开(公告)号：US20130208525A1
公开(公告)日：2013-08-15
申请号：US13563665
申请日：2012-07-31
申请人： Jack Z. Peng , David Fong
发明人： Jack Z. Peng , David Fong
IPC分类号： G11C17/16
CPC分类号： G11C17/165 , G11C17/16 , G11C17/18
摘要： A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-μA is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.
摘要翻译：非易失性存储单元仅使用两个晶体管，位选择和感测器件。每个单元进一步包括反熔丝装置，例如，当选择单元时，实施了场效应晶体管，该场效应晶体管被操作为表现得像反熔丝，并且施加了5.5伏和5-μA以下的适度的编程电压。因为在读取操作期间使用局部检测晶体管来检测编程并将其放大为列读出放大器，所以在薄栅氧化层中仅需要软的击穿。读数也只需要约一伏特的低电压。

49. 发明授权

US08503215B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US08503215B2
公开(公告)日：2013-08-06
申请号：US13526671
申请日：2012-06-19
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/36
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括转向元件和与该转向元件串联耦合的非易失性状态变化元件。转向元件和状态改变元件设置在垂直定向的支柱中。还提供其他方面。

50. 发明授权

US08477521B2 Fuse circuit and memory device including the same 有权
标题翻译：保险丝电路和包括其的存储器件
公开(公告)号：US08477521B2
公开(公告)日：2013-07-02
申请号：US12981290
申请日：2010-12-29
申请人： Kwi-Dong Kim , Jun-Gi Choi
发明人： Kwi-Dong Kim , Jun-Gi Choi
IPC分类号： G11C17/00 , G11C7/00 , G11C17/18 , G11C8/00
CPC分类号： G11C17/165 , G11C17/18 , G11C29/787
摘要： A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit.
摘要翻译：熔丝电路包括多个熔丝单元，放大单元和多个寄存器。放大单元被配置为顺序放大存储在熔丝单元中的数据。寄存器被配置为顺序地存储由放大单元放大的数据。

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