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41. 发明授权

US07486098B2 Integrated circuit testing method using well bias modification 失效
标题翻译：集成电路测试方法采用井偏置修正
公开(公告)号：US07486098B2
公开(公告)日：2009-02-03
申请号：US11876066
申请日：2007-10-22
申请人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
发明人： Anne Gattiker , David A. Grosch , Marc D. Knox , Franco Motika , Phil Nigh , Jody Van Horn , Paul S. Zuchowski
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/275 , G01R31/3008 , G01R31/31858
摘要： A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.
摘要翻译：一种用于测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。该方法通过修改测试过程中的良好偏差来提高IDDQ测试和诊断的分辨率。该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开布线的IC，允许在测试期间对阱电位进行外部控制（40）。通常，该方法依赖于使用阱偏压来改变晶体管阈值电压。

42. 发明申请

US20080029763A1 Transmission Circuit, Connecting Sheet, Probe Sheet, Probe Card, Semiconductor Inspection System and Method of Manufacturing Semiconductor Device 审中-公开
标题翻译：传输电路，连接片，探头片，探针卡，半导体检测系统及制造半导体器件的方法
公开(公告)号：US20080029763A1
公开(公告)日：2008-02-07
申请号：US11740301
申请日：2007-04-26
申请人： Susumu Kasukabe , Terutaka Mori , Yasunori Narizuka , Norio Chujo
发明人： Susumu Kasukabe , Terutaka Mori , Yasunori Narizuka , Norio Chujo
IPC分类号： H01L23/48 , G01R31/26 , H01L23/58 , H01L29/40
CPC分类号： G01R31/31905 , G01R1/0735 , G01R31/2874 , G01R31/2879 , G01R31/2889 , H01L2924/0002 , H01P3/081 , H01L2924/00
摘要： A probe sheet or a connecting sheet with good transmission characteristics and flexibility comprising contact terminals capable of contacting at a plurality of points and in high density, without applying damages on an electrode pad which is a contact subject is provided. Further, a high-speed transmission circuit capable of designing signal wirings with aligned impedance to have wide width even with a thin insulating film is achieved to provide a probe sheet or a connecting sheet with reduced loss of high-speed transmission signals. Moreover, the transmission circuit is applied to a probe card using a probe sheet, an inspecting method of (a method of manufacturing) a semiconductor device using the same, and a connecting sheet having an excellent high-frequency characteristic.
摘要翻译：提供了具有良好传输特性和柔性的探针片或连接片，包括能够在多个点和高密度下接触的接触端子，而不对作为接触物体的电极焊盘施加损伤。此外，实现了即使使用薄绝缘膜，能够设计具有均匀阻抗的宽度宽的宽度的高速传输电路，以提供具有降低的高速传输信号损失的探针片或连接片。此外，使用探针片将传输电路应用到探针卡，使用其的制造半导体器件的制造方法的检查方法以及具有优异的高频特性的连接片。

43. 发明授权

US07248988B2 System and method for reducing temperature variation during burn in 有权
标题翻译：烧伤过程中降低温度变化的系统和方法
公开(公告)号：US07248988B2
公开(公告)日：2007-07-24
申请号：US10791099
申请日：2004-03-01
申请人： Eric Chen-Li Sheng , David H. Hoffman , John Laurence Niven
发明人： Eric Chen-Li Sheng , David H. Hoffman , John Laurence Niven
IPC分类号： G06F15/00
CPC分类号： G01R31/2874 , G01K7/42 , G01R31/2879
摘要： Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.
摘要翻译：老化测试中降低温度变化的系统和方法。在一个实施例中，测量被测集成电路消耗的功率。测量与集成电路相关的环境温度。通过调整集成电路的体偏置电压来实现集成电路的期望结温。通过控制各个集成电路的温度，可以降低老化试验期间的温度变化。

44. 发明申请

US20070162799A1 Burn-in test signal generating circuit and burn-in testing method 审中-公开
标题翻译：老化测试信号发生电路和老化测试方法
公开(公告)号：US20070162799A1
公开(公告)日：2007-07-12
申请号：US11638694
申请日：2006-12-14
申请人： Shinya Kamada
发明人： Shinya Kamada
IPC分类号： G01R31/28
CPC分类号： G01R31/2879
摘要： A burn-in test signal path is provided in parallel with an ordinary signal path with respect to an analog circuit. A signal waveform converting circuit for converting a burn-in test signal of a digital waveform into a burn-in test signal of an analog waveform is provided in the burn-in test signal path. The ordinary signal path is controlled to switch over to the burn-in test signal path in the burn-in test of the analog circuit.
摘要翻译：提供与相对于模拟电路的普通信号路径并行设置的老化测试信号路径。在老化测试信号路径中提供用于将数字波形的老化测试信号转换为模拟波形的老化测试信号的信号波形转换电路。在模拟电路的老化测试中，控制普通信号路径切换到老化测试信号路径。

45. 发明申请

US20070091517A1 SYSTEM AND METHOD FOR REGENERATIVE BURN-IN 审中-公开
标题翻译：用于再生燃烧的系统和方法
公开(公告)号：US20070091517A1
公开(公告)日：2007-04-26
申请号：US11557912
申请日：2006-11-08
申请人： Michael Lucas , Eric Gilbert
发明人： Michael Lucas , Eric Gilbert
IPC分类号： H02H7/06
CPC分类号： G01R31/2879 , G01R31/2849 , G01R31/2891 , G01R31/40 , H02M3/3378
摘要： A regenerative load that includes an input configured to draw a specified current and an output configured to provide an output voltage and current is described. The regenerative load configured to maintain the output voltage to cause the regenerative load to draw the specified current from the unit under test. The output of the regenerative load is provided back to the input of the unit under test. The input current or voltage can be AC, DC, or a combination of AC and DC. The output current or voltage can be AC, DC, or a combination of AC and DC. In one embodiment, a thermal barrier is provided between a test chamber and a load chamber to allow converters under test to be operated at a test temperature while the regenerative loads are operated at a desired operational temperature.
摘要翻译：描述了包括被配置为绘制指定电流的输入和被配置为提供输出电压和电流的输出的再生负载。配置为保持输出电压以使再生负载从被测单元中抽出指定电流的再生负载。再生负载的输出返回到被测单元的输入端。输入电流或电压可以是AC，DC或AC和DC的组合。输出电流或电压可以是AC，DC或AC和DC的组合。在一个实施例中，在测试室和负载室之间提供热障，以允许被测试转换器在测试温度下操作，同时再生负载在期望的操作温度下操作。

46. 发明授权

US07180355B2 Level shifter circuit with stress test function 失效
公开(公告)号：US07180355B2
公开(公告)日：2007-02-20
申请号：US10944862
申请日：2004-09-21
申请人： Toshio Teraishi
发明人： Toshio Teraishi
IPC分类号： H03L5/00
CPC分类号： G09G3/006 , G01R31/2879 , G09G2310/0289 , G09G2330/08 , G11C5/145 , G11C29/12005
摘要： A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

47. 发明申请

US20060290372A1 Packaging reliability super chips 有权
标题翻译：包装可靠性超级芯片
公开(公告)号：US20060290372A1
公开(公告)日：2006-12-28
申请号：US11491216
申请日：2006-07-21
申请人： Jason Blanchet , James Crain , Charles Griffin , David Stone , Robert White
发明人： Jason Blanchet , James Crain , Charles Griffin , David Stone , Robert White
IPC分类号： G01R31/26
CPC分类号： G01R31/2856 , G01R31/2853 , G01R31/2855 , G01R31/2875 , G01R31/2879
摘要： A test chip module for testing the integrity of the flip chip solder ball interconnections between chip and substrate. The interconnections are thermally stressed through an array of individual heaters formed in a layer of chip metallurgy to provide a uniform and ubiquitous source of heat. Current is passed through the interconnection to be tested by a current supply circuit using one signal I/O interconnection and the voltage drop across the interconnection to be tested from the current passed therethrough is measured by a voltage measuring circuit connected through another signal I/O interconnection. Stress initiating cracking and degradation at the interconnection creates a measurable change in voltage drop across the interconnection.
摘要翻译：用于测试芯片和衬底之间的倒装芯片焊球互连的完整性的测试芯片模块。互连通过在芯片冶金层中形成的各个加热器的阵列进行热应力，以提供均匀且普遍存在的热源。电流通过互连使用一个信号I / O互连由电流供应电路进行测试，并且通过其中通过的电流将要测试的互连线上的电压降由通过另一个信号I / O连接的电压测量电路测量互连。在互连处的应力引发开裂和退化在互连上产生可测量的电压降变化。

48. 发明授权

US07138813B2 Probe station thermal chuck with shielding for capacitive current 失效
公开(公告)号：US07138813B2
公开(公告)日：2006-11-21
申请号：US10626903
申请日：2003-07-25
申请人： Clarence E. Cowan , Paul A. Tervo , John L. Dunklee
发明人： Clarence E. Cowan , Paul A. Tervo , John L. Dunklee
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28
CPC分类号： G01R31/2874 , G01R1/18 , G01R31/2855 , G01R31/2862 , G01R31/2865 , G01R31/2879 , H01L35/00 , H01L35/32
摘要： To reduce noise in measurements obtained by probing a device supported on surface of a thermal chuck in a probe station, a conductive member is arranged to intercept current coupling the thermal unit of the chuck to the surface supporting the device. The conductive member is capacitively coupled to the thermal unit but free of direct electrical connection thereto.

49. 发明申请

US20060197548A1 DEVICE FOR PROBE CARD POWER BUS VOLTAGE DROP REDUCTION 失效
标题翻译：用于探头卡电源总线电压降低的装置
公开(公告)号：US20060197548A1
公开(公告)日：2006-09-07
申请号：US11242864
申请日：2005-10-05
申请人： Raphael Robertazzi
发明人： Raphael Robertazzi
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , G01R31/31721 , G01R31/31723
摘要： Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.
摘要翻译：将结构测试图案应用于被测器件（DUT）的降噪是通过探针卡上的电容器“升压器”旁路网络实现的，其中电容器被充电到高得多的电压V增益比DUT的电源电压VDD。将电容器充电到电压NxVDD允许破坏器网络存储N倍常规配置的电容网络的电荷，并有效提供原始网络在相同物理空间中的电容N倍。

50. 发明申请

US20050285612A1 Apparatus for measuring DC parameters in a wafer burn-in system 审中-公开
标题翻译：用于测量晶片老化系统中的直流参数的装置
公开(公告)号：US20050285612A1
公开(公告)日：2005-12-29
申请号：US10875121
申请日：2004-06-23
申请人： Jang-wook Heo
发明人： Jang-wook Heo
IPC分类号： G01R31/26 , G01R31/28 , G01R31/30
CPC分类号： G01R31/2879 , G01R31/3004
摘要： The present invention relates to an apparatus for measuring DC parameters which has a simplified hardware constitution of a DC block by simplifying the connection relationship of the DC block and DUTs for measuring DC parameters in a wafer burn-in system, and which can cause the processing time for measuring the DC parameters to be reduced by making it possible to receive more DUTs. According to the present invention, there is provided an apparatus for measuring DC parameters in a wafer burn-in system, comprising: n same circuits for measuring the DC parameters, wherein the n circuits are connected one-to-one to n switching means (DRy), and each of the n circuits is connected to eighteen (18) DUTs (Devices Under Test) through each of the n switching means (DRy). According to such a present invention, the constitution can be advantageously minimized in the hardware relatively compared with an apparatus for measuring DC parameters provided in the conventional wafer burn-in system. In addition, by increasing more than twice the number of the DUTs which can be treated by the single process, the time for measuring the DC parameters in the wafer burn-in process can be effectively reduced.
摘要翻译：本发明涉及用于测量直流参数的装置，其通过简化DC块和DUT的连接关系来简化DC块的硬件结构，用于测量晶片老化系统中的直流参数，并且可以导致处理通过使得可以接收更多的DUT来测量要减小的DC参数的时间。根据本发明，提供了一种用于测量晶片老化系统中的DC参数的装置，包括：n个用于测量DC参数的相同电路，其中n个电路一对一连接到n个切换装置（ DRy），并且n个电路中的每一个通过n个切换装置（DRy）中的每一个连接到十八（18）个DUT（被测设备）。根据这样的本发明，与用于测量在常规晶片老化系统中提供的DC参数的装置相比，可以有利地在硬件中最小化该结构。另外，通过增加可以通过单次处理的DUT的数量的两倍以上，可以有效地减少用于测量晶片老化过程中的DC参数的时间。

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