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41. 发明授权

US6067254A Method to avoid program disturb and allow shrinking the cell size in split gate flash memory 有权
标题翻译：避免程序干扰的方法，并允许在分裂门闪存中缩小单元大小
公开(公告)号：US6067254A
公开(公告)日：2000-05-23
申请号：US314590
申请日：1999-05-19
申请人： Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Jack Yeh
发明人： Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Jack Yeh
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/10
摘要： A method of programming split gate flash memory cells which avoids erroneously programming non selected cells and allows the cell size and the array size to be shrunk below previously realizable limits. For N channel cells with the control gates connected to word lines and drains connected to bit lines a negative voltage is supplied between the non selected word lines and ground potential. For P channel cells with the control gates connected to word lines and drains connected to bit lines a positive voltage is supplied between the non selected word lines and ground potential. This allows the minimum length of the control gate over the channel region to be reduced below previously allowable limits and still prevent programming of non selected cells. This also allows cell size and array size to be reduced.
摘要翻译：编程分裂栅极闪存单元的方法，其避免错误地编程未选择的单元，并允许单元尺寸和阵列尺寸缩小到先前可实现的极限以下。对于具有连接到字线的控制栅极和连接到位线的漏极的N沟道单元，在非选择字线和地电位之间提供负电压。对于具有连接到字线的控制栅极和连接到位线的漏极的P沟道单元，在非选择字线和地电位之间提供正电压。这允许将通道区域上的控制栅极的最小长度减小到低于先前允许的极限，并且仍然阻止对未选择的单元进行编程。这也可以减小单元格尺寸和阵列大小。

42. 发明授权

US6017795A Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash 失效
标题翻译：埋入源的方法，以收缩电池尺寸并增加分流栅闪电中的耦合比
公开(公告)号：US6017795A
公开(公告)日：2000-01-25
申请号：US72996
申请日：1998-05-06
申请人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
发明人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.
摘要翻译：提供了一种用于形成具有减小的尺寸，部分埋入的源极线，增加的源耦合比，改进的可编程性和整体增强性能的分裂栅极快闪存储器单元的方法。分裂门电池还具有减小的尺寸和改进的性能。源极线形成在源极区域上的衬底中的沟槽中。沟槽壁提供增加的源耦合，并且没有门鸟的喙与沟槽一起收缩细胞尺寸。通过浮动栅极和控制栅极之间的隔间氧化物，通过更有利的热电子注入也可以提高可编程性。

43. 发明授权

US07951670B2 Flash memory cell with split gate structure and method for forming the same 有权
标题翻译：具有分离栅结构的闪存单元及其形成方法
公开(公告)号：US07951670B2
公开(公告)日：2011-05-31
申请号：US11368714
申请日：2006-03-06
申请人： Chen-Ming Huang , Hung-Cheng Sung , Wen-Ting Chu , Chang-Jen Hsieh , Ya-Chen Kao
发明人： Chen-Ming Huang , Hung-Cheng Sung , Wen-Ting Chu , Chang-Jen Hsieh , Ya-Chen Kao
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885
摘要： A split gate memory cell. A floating gate is disposed on and insulated from a substrate comprising an active area separated by a pair of isolation structures formed therein. The floating gate is disposed between the pair of isolation structures and does not overlap the upper surface thereof. A cap layer is disposed on the floating gate. A control gate is disposed over the sidewall of the floating gate and insulated therefrom, partially extending to the upper surface of the cap layer. A source region is formed in the substrate near one side of the floating gate.
摘要翻译：分离门存储单元。浮置栅极设置在基板上并与基板绝缘，该基板包括由形成在其中的一对隔离结构分开的有源区域。浮栅设置在一对隔离结构之间，并且不与其上表面重叠。盖层设置在浮动栅上。控制栅极设置在浮动栅极的侧壁上并与其绝缘，部分地延伸到盖层的上表面。源极区域形成在靠近浮动栅极一侧的衬底中。

44. 发明申请

US20080121975A1 Split-gate memory cells and fabrication methods thereof 有权
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080121975A1
公开(公告)日：2008-05-29
申请号：US11592290
申请日：2006-11-03
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

45. 发明申请

US20080105917A1 Split-gate memory cells and fabrication methods thereof 失效
标题翻译：分离栅存储单元及其制造方法
公开(公告)号：US20080105917A1
公开(公告)日：2008-05-08
申请号：US11785382
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Wen-Ting Chu , Chen-Ming Huang , Ya-Chen Kao , Shih-Chang Liu , Chi-Hsin Lo , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521
摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A top level of the active regions is lower than a top level of the isolation regions. A pair of floating gates is disposed on the active regions and aligned with the isolation regions, wherein a passivation layer is disposed on the floating gate to prevent thinning from CMP. A pair of control gates is self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates is disposed on the outer sidewalls of the pair of control gates along the second direction.
摘要翻译：分离栅存储单元及其制造方法。分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，两个相邻的隔离区域限定具有一对漏极和源极区域的有源区域。活动区域的顶层低于隔离区域的顶层。一对浮置栅极设置在有源区上并与隔离区对准，其中钝化层设置在浮栅上以防止CMP变薄。一对控制栅极与浮动栅极自对准，并沿第二方向设置在浮动栅极上。源极线沿第二方向设置在该对控制栅极之间。一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。

46. 发明申请

US20070181936A1 NOVEL ARCHITECTURE TO MONITOR ISOLATION INTEGRITY BETWEEN FLOATING GATE AND SOURCE LINE 审中-公开
标题翻译：浮动门和源线之间的监视隔离整合的新建筑
公开(公告)号：US20070181936A1
公开(公告)日：2007-08-09
申请号：US11736050
申请日：2007-04-17
申请人： Chang-Jen Hsieh , Hung-Cheng Sung , Te-Hsun Hsu
发明人： Chang-Jen Hsieh , Hung-Cheng Sung , Te-Hsun Hsu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L22/34 , H01L27/11521 , H01L29/40114 , H01L2924/0002 , H01L2924/00
摘要： A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.
摘要翻译：实现了在制造存储器件中形成浮栅隔离测试结构的新方法。该方法包括提供基底。栅极氧化层形成在衬底上。沉积栅极氧化物层的浮栅导体层。图案化浮栅导体层以暴露用于计划源区的衬底。将离子注入到暴露的基底中以形成源区。接触结构形成于源区。接触结构形成于浮栅导体层。

47. 发明授权

US07102919B1 Methods and devices for determining writing current for memory cells 有权
标题翻译：用于确定存储器单元写入电流的方法和装置
公开(公告)号：US07102919B1
公开(公告)日：2006-09-05
申请号：US11078171
申请日：2005-03-11
申请人： Hung-Cheng Sung , Der-Shin Shyu
发明人： Hung-Cheng Sung , Der-Shin Shyu
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.
摘要翻译：确定存储单元写入电流的方法。将第一参考电流施加到第一操作线以将存储器单元切换到第一状态。第二参考电流被施加到穿过第一操作线的第二操作线，以将存储器单元切换到第二状态。根据第一比率和第一参考电流获得第一写入电流。根据第二比例和第二参考电流获得第二写入电流。通过将第一写入电流施加到第一操作线并将第二写入电流施加到第二操作线来编程存储器单元。

48. 发明授权

US06753569B2 Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation 有权
标题翻译：在具有自对准隔离的分离栅闪光中制造非微笑效果结构的方法
公开(公告)号：US06753569B2
公开(公告)日：2004-06-22
申请号：US10029622
申请日：2001-12-31
申请人： Yai-Fen Lin , Chang Song Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Juang-Ke Yeh
发明人： Yai-Fen Lin , Chang Song Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Juang-Ke Yeh
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A method is provided for forming a split-gate flash memory cell having a shallow trench isolation without the intrusion of a “smiling” gap near the edge of the trench encompassing the first polysilicon layer. This is accomplished by forming two conformal layers lining the interior walls of the trench. An exceptionally thin nitride layer overlying the first conformal oxide layer provides the necessary protection during the oxidation of the first polysilicon layer so as to prevent the “smiling” effect normally encountered in fabricating ultra large scale integrated circuits.
摘要翻译：提供了一种用于形成具有浅沟槽隔离的分离栅极闪存单元的方法，而不会在包围第一多晶硅层的沟槽的边缘附近侵入“微笑”间隙。这通过在沟槽的内壁上形成两个共形层来实现。覆盖第一保形氧化物层的非常薄的氮化物层在第一多晶硅层的氧化期间提供必要的保护，以防止在制造超大规模集成电路时通常遇到的“微笑”效应。

49. 发明授权

US06569736B1 Method for fabricating square polysilicon spacers for a split gate flash memory device by multi-step polysilicon etch 有权
标题翻译：通过多步多晶硅蚀刻制造用于分离栅极闪存器件的方形多晶硅间隔物的方法
公开(公告)号：US06569736B1
公开(公告)日：2003-05-27
申请号：US10076668
申请日：2002-02-14
申请人： Cheng-Yuan Hsu , Hung-Cheng Sung , Su-Chang Chen , Han-Ping Chen , Chia-Ta Hsieh , Der-Shin Shyu
发明人： Cheng-Yuan Hsu , Hung-Cheng Sung , Su-Chang Chen , Han-Ping Chen , Chia-Ta Hsieh , Der-Shin Shyu
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/6656 , H01L29/66825
摘要： A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.
摘要翻译：描述了通过多步多晶硅蚀刻工艺在分裂栅极闪存器件上形成方形多晶硅间隔物的方法。该方法可以通过在闪存器件结构上沉积多晶硅层，然后在多晶硅层的顶部上沉积牺牲层，例如氧化硅来进行。在主蚀刻步骤期间，牺牲层具有比多晶硅层更慢的蚀刻速率。覆盖闪存器件的牺牲层然后被去除，同时侧壁上的牺牲层保持完整。然后将覆盖在闪速存储器件上的多晶硅层蚀刻掉，随后除去所有残余牺牲层的步骤。然后蚀刻暴露的多晶硅层以在分裂栅极闪存器件上限定方形多晶硅间隔物。

50. 发明授权

US06482700B2 Split gate field effect transistor (FET) device with enhanced electrode registration and method for fabrication thereof 有权
标题翻译：具有增强的电极配准的分离栅场效应晶体管（FET）器件及其制造方法
公开(公告)号：US06482700B2
公开(公告)日：2002-11-19
申请号：US09725984
申请日：2000-11-29
申请人： Han-Ping Chen , Hung-Cheng Sung
发明人： Han-Ping Chen , Hung-Cheng Sung
IPC分类号： H01L218232
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66553
摘要： Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication there is employed a patterned mask layer as an etch mask layer for forming from a blanket floating gate electrode material layer a floating gate electrode. At least a portion of the patterned mask layer is then laterally etched to completely expose an edge of the floating gate electrode prior to forming over the floating gate electrode and the edge of the floating gate electrode an inter-gate electrode dielectric layer having formed thereupon a control gate electrode. The method contemplates a split gate field effect transistor (FET) device fabricated in accord with the method. The resulting split gate field effect transistor (FET) device has an enhanced control gate electrode to floating gate electrode registration.
摘要翻译：在用于在半导体集成电路微电子制造中制造分裂栅极场效应晶体管（FET）的方法中，采用图案化掩模层作为用于从橡皮布浮栅电极材料层形成浮栅电极的蚀刻掩模层。然后在图案化掩模层的至少一部分被横向蚀刻之前，以在形成浮栅和浮栅之间的栅极电极介质层之前形成的栅间电极介电层控制栅电极。该方法考虑了根据该方法制造的分裂栅极场效应晶体管（FET）器件。所产生的分离栅场效应晶体管（FET）器件具有增强的控制栅电极到浮栅电极配准。

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