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    • 46. 发明申请
    • Silicon Wafer Surface Defect Evaluation Method
    • 硅晶片表面缺陷评估方法
    • US20070044709A1
    • 2007-03-01
    • US11467411
    • 2006-08-25
    • Wataru ItouTakeshi HasegawaTakaaki Shiota
    • Wataru ItouTakeshi HasegawaTakaaki Shiota
    • C30B15/00C30B21/06C30B27/02C30B28/10C30B30/04
    • H01L22/12
    • There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist. A silicon wafer surface defect evaluation method according to the present invention is characterized by comprising: a rapid heat treatment step of applying a heat treatment to a silicon wafer cut out from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C./second; and a step of using a surface photo voltage method to calculate a minority carrier diffusion length on the wafer surface, thereby detecting a region on the wafer surface in which small COP's which cannot be detected at least by a particle counter exist.
    • 提供了能够容易地检测存在小晶体缺陷的区域的硅晶片表面缺陷评估方法。 根据本发明的硅晶片表面缺陷评估方法的特征在于包括:快速热处理步骤,在可以在温度为氮化硅的气氛中从硅单晶锭切出的硅晶片进行热处理 将升温速度从室温升温至不低于1170℃至低于硅熔点的温度,将硅晶片在处理温度下保持1至120秒,然后冷却 硅晶片以10〜100℃/秒的降温速度至室温; 以及使用表面光电压法来计算晶片表面上的少数载流子扩散长度的步骤,从而检测晶片表面上至少存在无法检测到的小的COP的区域。
    • 48. 发明授权
    • Wire harness design aiding apparatus, method and computer readable recording medium storing program
    • 线束设计辅助设备,方法和计算机可读记录介质存储程序
    • US07164957B2
    • 2007-01-16
    • US10737759
    • 2003-12-18
    • Shinji TsuchiyaKohki NagakuraTakeshi Hasegawa
    • Shinji TsuchiyaKohki NagakuraTakeshi Hasegawa
    • G06F19/00
    • G06F17/509G06F2217/36
    • A wire harness design aiding apparatus for designing a wire harness includes: a display unit for three dimensionally displaying an object on which the wire harness is to be arranged and the wire harness on a CAD display in a state that two points of the wire harness is constrained; a guide line setting unit for setting, based on a constraining direction of the wire harness with respect to the object, guide lines which are intersection points of a guide plane which is parallel to the wiring jig plate and extends passing the axial line of the main line and an outer surface of the main line, and displaying the guide line on the CAD display; and a branch line setting unit for branching out the branch line from a position on the main line in a direction along the guide plane.
    • 一种用于设计线束的线束设计辅助装置,包括:显示单元,用于在线束的两个点处的状态下三维地显示要布置线束的物体和线束在CAD显示器上 受限的 引导线设定单元,其基于线束相对于物体的约束方向,作为与导线夹具板平行且延伸通过主体的轴线延伸的导向面的交点的引导线 线和主线的外表面,并且在CAD显示器上显示引导线; 以及分支线设置单元,用于沿着所述导向平面的方向从所述主线上的位置分支所述分支线。