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    • 41. 发明授权
    • Low power high speed pipeline ADC
    • 低功耗高速流水线ADC
    • US08451160B1
    • 2013-05-28
    • US13109320
    • 2011-05-17
    • Hao ZhouYonghua SongTao ShuiJie JiangSong Chen
    • Hao ZhouYonghua SongTao ShuiJie JiangSong Chen
    • H03M1/38
    • H03M1/002H03M1/1215H03M1/124H03M1/167
    • In accordance with the teachings described herein, systems and methods are provided for a time-interleaved pipeline analog to digital converter. An example pipeline analog to digital converter may include passive sampling circuits and a multiplying digital to analog converter circuit. A first passive sampling circuit includes an input terminal coupled to an analog input signal, and outputs a first sample voltage that is responsive to the analog input signal. A second passive sampling circuit includes an input terminal coupled to the analog input signal, and outputs a second sample voltage that is responsive to the analog input signal. The first and second passive sampling circuits are clocked such that the first sample voltage and the second sample voltage are time-interleaved. A multiplying analog to digital converter (MDAC) circuit receives the time-interleaved first and second sample voltages from the first and second passive sampling circuits and processes the time-interleaved first and second sample voltages to generate a residue output voltage.
    • 根据本文描述的教导,为时间交错流水线模数转换器提供了系统和方法。 示例性管线模数转换器可以包括无源采样电路和乘法数模转换器电路。 第一无源采样电路包括耦合到模拟输入信号的输入端,并且输出响应于模拟输入信号的第一采样电压。 第二无源采样电路包括耦合到模拟输入信号的输入端,并且输出响应于模拟输入信号的第二采样电压。 第一和第二无源采样电路被计时,使得第一采样电压和第二采样电压是时间交织的。 乘法模数转换器(MDAC)电路接收来自第一和第二无源采样电路的时间交错的第一和第二采样电压,并处理时间交错的第一和第二采样电压以产生残余输出电压。